Setting the ramp slope in a 10bit ADC simulation

[neo]

AD convertor simulation

when i simulate the static performance of the 10bit adc (no missing code gurantee, DNL...), is it a must to set the ramp slope to be ajusted to provide one output in a sampling period?
can i simulate the adc 1LSBjump/2sampling period(Ts), or 1/3Ts, dose it matter? why?

 

[noiseless]

AD convertor simulation

does not matter. just make sure all the conversion point you can sampled

 

[elcielo]

Re: AD convertor simulation

ADIsimADC™ Virtual Evaluation Board

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https://www.analog.com/Analog_Root/...e/matlab_license.html?adc=Matlab_Support2.zip

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[neo]

Re: AD convertor simulation

does not matter. just make sure all the conversion point you can sampled

ur "make sure the conversion point" means no missing code guranteed? but it is really a coarse simulation, i think, how to estimate the DNL, INL, although it requires a plenty of time to do so.

 

[Btrend]

Re: AD convertor simulation

there is a method called histogram method, which need more points in every code word. usually (4 ponits)/(1 code) are used to simulate static characteristics.
u can search in this forum about ADC test , there exist a IEEE standard(1241) and DYNAD document talking about the testing of ADC.

 

[neo]

Re: AD convertor simulation

there is a method called histogram method, which need more points in every code word. usually (4 ponits)/(1 code) are used to simulate static characteristics.
u can search in this forum about ADC test , there exist a IEEE standard(1241) and DYNAD document talking about the testing of ADC.

yeah, u r perfectly right, but can i say if my adc can work with 1point/1code, it is better than the adc can work with more than 1point/1code (e.g. 2points/1code or more) only.

and, if i choose (4 ponits)/(1 code) as u said for my 10bit 40MegaHz adc, i must run a 4*25ns*1024code=102400ns=102.2us trans simulation, that's maybe a nightmare when set the accuracy "conservative".

 

[Btrend]

Re: AD convertor simulation

1.in talking about "static" , time is long respect to variable change.
in talking about "dynamic", time is short respect to variable change.

2. if u want to increase ur simulation speed, some kind of macro modeling is needed, to simplified ur whole chip complexity.

3.anyway, as compared to the debugging cycle after chip is back, what u spend in ur simulation is pretty "short", u will probably know what I mean if ur chip is back and something is wrong but u can not figure out what is going on .