popsika
Newbie level 2
![Newbie level 2](/styles/images/ranks/alevel2.gif)
Hi!
I'm quite a newbie in using design compiler. I have parts in my design, which are not present in the actual later circuit, but which I need for the simulation. Because of that, these paths do not need to be considered in the STA. Therefore I marked them as false paths.
But now I have the problem, that some paths are starting in my "real" circuit and ending in my "fake" circuit. So I can not declare the whole path as a false path. Is there a possibility to mark all paths inside a component (I'm using VHDL) as "ideal" in terms of gate and wire delays? I just found the ideal attribute which seems to be used for clock paths.
Thanks in advance!
I'm quite a newbie in using design compiler. I have parts in my design, which are not present in the actual later circuit, but which I need for the simulation. Because of that, these paths do not need to be considered in the STA. Therefore I marked them as false paths.
But now I have the problem, that some paths are starting in my "real" circuit and ending in my "fake" circuit. So I can not declare the whole path as a false path. Is there a possibility to mark all paths inside a component (I'm using VHDL) as "ideal" in terms of gate and wire delays? I just found the ideal attribute which seems to be used for clock paths.
Thanks in advance!