henle
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hi
i am a new in fpga programming so if anyone could help me out in clearing this confusion between simulink clock period,fpga clock period(sysgen token) and sample period in respective blocks of the design????
for example if my starter board spartan 3 has a clock oscillator of 50 Mhz so will my fpga clock period be 20ns or something else?
if yes then wat would be the simulink system period in the xilinx sysgen token and what wud be its relation to the sample periods of other blocks of my design????
i am a new in fpga programming so if anyone could help me out in clearing this confusion between simulink clock period,fpga clock period(sysgen token) and sample period in respective blocks of the design????
for example if my starter board spartan 3 has a clock oscillator of 50 Mhz so will my fpga clock period be 20ns or something else?
if yes then wat would be the simulink system period in the xilinx sysgen token and what wud be its relation to the sample periods of other blocks of my design????