Set pin load constraint

Status
Not open for further replies.
R

ruanwang

Junior Member level 1
Junior Member level 1
Joined
Dec 21, 2014
Messages
18
Helped
1
Reputation
2
Reaction score
1
Trophy points
3
Activity points
108
Hello guys,

My friend ask me 3 questions, but I'm not sure to answer him.
1) What are the important constraints in a SDC file? why?
2) What are pin load constraints? why we use it?
3) we need to TAPEOUT in 4 days & we have both SETUP & HOLD violations – which one we fix first & why?

Please give me your view about them.
Thank you, BR.
 

ruanwang said:
1) What are the important constraints in a SDC file? why?
Click to expand...
Fan-out. This should make sure, that fan-in of connected gates doesn't exceed the permissible fan-out of an output node.

ruanwang said:
2) What are pin load constraints? why we use it?
Click to expand...
Same, but given in pF (10-12 Farad). Max. allowed load capacitance - in order not to exceed pin output current resp. power rating and slew rate.

ruanwang said:
3) we need to TAPEOUT in 4 days & we have both SETUP & HOLD violations – which one we fix first & why?
Click to expand...
Actually both. Because of short time, I'd begin to repair the SETUP violations, perhaps the HOLD violations do not apply - if you are lucky.
And why? If SETUP time isn't respected, data aren't stored at all. Perhaps HOLD time is still enough - or can be prolonged by software changes (by adding another clock cycle). A relatively good chance to read back correct data.
 

hi erikl,
thanks for reply.
1) fanout is important. But how about clock definition?
2) I'm sorry that I cant catch up yr mean. could you explain more?
3) my friends said that we should choose HOLD. Because, we can fix SETUP by relax some margin (Ex: clock uncertainty, clock cycle...), but HOLD is not. How about yr idea?
 

ia anyone has other idea? please teach me :(
 

Status
Not open for further replies.

Similar threads