[SOLVED] Set all bits to 1 in Verilog

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nervecell_23

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For a signal whose word-length is a PARAMETER, how to set all its bits to 1 in Verilog?

Using '1 is not supported in some synthesis tool because it's a systemVerilog feature...

Thanks!
 
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nervecell_23 said:
For a signal whose word-length is a GENERIC, how to set all its bits to 1 in Verilog?

Using '1 is not supported in some synthesis tool because it's a systemVerilog feature...

Thanks!
Click to expand...
You mean a parameter (Generic is VHDL).

assign some_signal = {width_paramter{1'b1}};
 
Dave, how about :
assign some_signal = -'b1;

Also, if the signal width is more than 32, will the "~0" assignment still apply? If yes, how does verilog actually parse the code and resolve it?

Thanks
Leo
 
layowblue said:
Also, if the signal width is more than 32, will the "~0" assignment still apply? If yes, how does verilog actually parse the code and resolve it?
Click to expand...

I tried it with Vivado's simulator, which is only Verilog 2001 complient and yes it worked with a 128-bit signal. I don't think Verilog cares how may bits you put in a bit vector. In the case of integer Verilog is only defined for 32-bits.
 
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