Serial in Parallel out shift register. VHDL CODE

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THEDOGFATHER89

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Hi guys this is my first post.

In my programme i have to Design a Serial In, Parallel Out, (SIPO) sift register with a Clock and Data input (both single
lines and an 8-bit parallel output Q. Serial data is accepted at the shift register input on a rising
clock edge and is placed in the least significant bit – the other 7 bits of existing data shift to left.
The most significant data bit is discarded once each new bit is accepted.

Im having a bit of trouble with the code to discard the most significant bit. Any help will be greatly appreciated thanks

Here is my code so far

Code: 
----------------------------------------------------------------------------------
--SIMPLE GENERATE AND COMPONENT
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity SIPO is
Generic(N:integer :=8);
port(sin,clk :in STD_LOGIC;
sout : out STD_LOGIC );

end SIPO;

architecture SHIFT of SIPO is

component d_flip_flop is
port(D,clk :in STD_LOGIC;
Q,nQ : out STD_LOGIC);

end component d_flip_flop; 

signal Z: std_logic_vector (N downto 0);

begin

z(0)<=sin;
Q1:for I in 0 to N-1 generate
d_flip_flopx:d_flip_flop port map(clk,z(i),z(i+1),open);
end generate;

sout<=z(8);

end SHIFT;
 
Last edited by a moderator:

First of all, you don't need to "discard" the MSB; when you shift D7 to Q7, the old Q7 just 'disappears'.

But a bigger problem for you is that you've used 'positional mapping', which is a sure-fire way to shoot yourself in the foot. I STRONGLY advise you to use 'nominal mapping' (e.g., clk=> clk)which might take a little more effort but will avoid errors like you have (You've mapped clk to D and vice versa in your code when I THINK what you want is to map Q(z-1) to D).

Another error you've got is you've generated an 8-bit register, but you're assign a 9th bit, z(8) to sout, and z(8) never gets a value. Maybe you want sout <=z(7)? Not sure what you're trying to do...
 
Thanks for the reply barry ive made the changes to the code that you suggested but ive to use positional mapping.

Here is the code i have now. Do i require anymore changes?

Code: 
----------------------------------------------------------------------------------
--SIMPLE GENERATE AND COMPONENT
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity SIPO is
Generic(N:integer :=8);
port(sin,clk :in STD_LOGIC;
sout : out STD_LOGIC );

end SIPO;

architecture SHIFT of SIPO is

component d_flip_flop is
port(clk,D :in STD_LOGIC;
Q,nQ : out STD_LOGIC);

end component d_flip_flop; 

signal Z: std_logic_vector (N downto 0);

begin

z(0)<=sin;
Q1:for I in 0 to N-1 generate
d_flip_flopx:d_flip_flop port map(clk,z(i),z(i+1),open);
end generate;

sout<=z(7);

end SHIFT;
 

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