serial communication in FPGA

[xanuz]

anyone plz tell me how a data stream from a PC through serial port can be correctly received in a spartan 3E FPGA (in asynchronous mode)? do we have to design separate circuits or are there any built in UARTs or something else in the FPGA board?
where does the serial data gets stored ?

and how do i actually time the clk at the FPGA to recieve the data from the PC?

can anyone spread light into this matter ...... please help me...!!!
(can anyone provide the vhdl code for desired frequency generation)

 

[lucbra]

Hello,

An FPGA in its nature is a programmable device. Therefore, it is very much possible to achieve what you want to do, but you will need to code it yourself.
Of course you can use pre coded blocks and build them together, but the nice thing about an FPGA is the fact that you can streamline the functions to your needs.

To answer your questions:
- I haven't seen any modern FPGA (Xilinx, Altera, Actel, Lattice) that have built-in UART
- you don't store your serial data, you process it as soon as you can, but if you want you can use memory block to temporary store your data (the blocks are SRAM thus volatile
- I don't understand your question about the time.. I'm just guessing: RS-232 (UART) has no separate clock, this is generated in the FPGA but dividing the input clock signal (usually coming from a crystal oscillator or the like) to a secondary clock signal at the desired baud rate (x8)

I hope this sheds some light at your questions

Regards

(you can always push the 'helped' button to appreciate my answers)

 

[falloutmx]

as serial port is a low-speed port,we don't need anything to store it.it seems you should learning about baudrate and uart.

 

[scanman]

xanuz,

Check out this post:



You will find UART VHDL in my attachment.

Cheers,
Scanman

 

[xanuz]

hey guys!!! thanx for helping.....from your comments i have found that i still have to study a lot on UART and baud generator for this serial communication ..... actually i would study baud generator for now .......................I have to generate a clk signal of required baud rate (frequency) from 50MHz system clk , right?

 

[lucbra]

I assume you have moderate VHDL (or Verilog) knowledge.
Then it shouldn't be that difficult to pick up some uart examples and study how these are designed. Usually these examples derive a low frequency clock from 25MHz or 50MHz (this is just a simple divider)
You can use the internal PLL to do a first division, and divide further down to the desired clock signal.

Good luck

 

[xanuz]

hey guys !!! this is embarassing but i couldn't find a suitable or self-explanatory VHDL codes for a Baud Rate Generator....would you guys please post a vhdl code for a baud rate generator ... or at least explain how to implement one!!!

so sorry for my ignorance but i couldnt understand the ones in the internet...

 

[lucbra]

Hi there,

I can recommend https://www.alse-fr.com/free_ips.php.
Look for RS-232. This implementation is very well documented.
It gives you besides the baud rate generation (at the end of the article) also the implementation of the UART.

Good luck

 

[scanman]

xanuz,

I posted the VHDL code with extra documentation to help you understand it:



Look for zip file attachment.

Cheers,
Scanman

 

[xanuz]

hey this is how i have designed a simple baud generator!!! It generates a 307.2khz clk for oversampling the received signal at 16 times the actual baud rate (19.2 kbps)


please comment on whether this is the right way !!
thnx

 

[lucbra]

Hi Xanux,

Some remarks,

- your process doesn't have a reset condition. This is not so nice for an FPGA.
- out_clk doesn't have an initiate state, and therefore It wont toggle. Even if you have added an initial state in the signal definition, it is allways better to force an initial in the reset condition.

I would change your process to:

proc_divider : process (clk, reset)  -- a good habit to label your processes
begin
   if reset = '0' then    -- asserted low
      clk_out <= '0';
   elsif rising_edge (clk) then    -- use rising_edge i.s.o. 'event
      if (clk_count < clk_divider then
         clk_count <= clk_count + count_inc;
      else
         out_clk <= not out_clk;
         clk_count <= (others => '0);   -- if there is a special reason to start at 1 then change this line
      end if;
   end if;
end process proc_divider;

regards

 

[xanuz]

Hi Xanux,

Some remarks,

- your process doesn't have a reset condition. This is not so nice for an FPGA.
- out_clk doesn't have an initiate state, and therefore It wont toggle. Even if you have added an initial state in the signal definition, it is allways better to force an initial in the reset condition.



regards

thank u lucbra
i m just a beginner in VHDL programming ......hence i always need your help...

 

[xanuz]

heres what i did to transfer a byte of data into the FPGA Spartan 3E kit through the serial port (using MATLAB).......the simulation seems fine but however the actual implementation doesnt work ..

can anyone look into it ? I really cant figure out whats wrong !!!

MATLAB code:

% test serial communication 
s = serial ('COM1','BaudRate',1,'DataBits',8);
fopen (s);
fprintf (s,'%c', 1 );
fclose(s);
clear s;

 

[falloutmx]

what is your top module when implement?
uart_tb.vhd is only used for simulation.

 

[xanuz]

what is your top module when implement?
uart_tb.vhd is only used for simulation.

uart.vhd is the top module itself. I use Xilinx to directly program it into the spartan 3E board itself.