Sequential Circuit

Basit Mehmood · Jan 12, 2023

What happened if we use blocking assignment in sequential circuit like flip-flop?
I mean is following code correct or not?

Code Verilog - [expand]
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module dff (q, qn, d, clk);
   input d, clk;
   output q, qn;
   reg q, qn;
   always @(posedge clk)
      begin
         q = d;
         qn = ~d;
      end
endmodule

ThisIsNotSam · Jan 12, 2023

conceptually, it is wrong.
depending on the synthesis tool, it might synthesize correctly.

FvM · Jan 12, 2023

1. What do you want to achieve? Just playing around?
There's a reason, why design rules say use non-blocking in clocked always block and blocking in combinational. For a comprehensive explanation, read this classical paper http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA_rev1_2.pdf

2. In this special case, non-blocking assignments make no difference. That's because the assigned variable q and qn aren't appearing on RHS of other expressions below the assignment.

3. Sometimes you want intermediate combinational results assigned to a variable inside a clocked always block. In this case, blocking assignments may be used intentionally.

Sequential Circuit

Basit Mehmood

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ThisIsNotSam

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andre_luis

FvM

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Code Verilog - [expand]
1 2 3 4 5 6 7 8 9 10	module dff (q, qn, d, clk); input d, clk; output q, qn; reg q, qn; always @(posedge clk) begin q = d; qn = ~d; end endmodule

Sequential Circuit

Basit Mehmood

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ThisIsNotSam

Advanced Member level 5

FvM

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