karthikeie
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Sequence in system verilog
Hi there,
I have some trouble in understanding the working of sequence endsequence in system verilog. Please explain me about the sequence part. What is that ## operator meant for? and what if i change the values???
Thanks in advance...
module sequence_test();
reg a,b,c;
reg clk = 0;
sequence abc;
@(posedge clk) a ##1 b ##1 c;
endsequence
always @ (posedge clk)
begin
@ (abc) $display ("@%g ABC all are asserted", $time);
end
initial begin
$monitor("@%g clk %b a %b b %b c %b", $time, clk, a, b, c);
repeat (2) begin
#2 a = 1;
#2 b = 1;
#2 c = 1;
#2 a = 0;
b = 0;
c = 0;
end
#2 $finish;
end
always #1 clk = ~clk;
endmodule
Hi there,
I have some trouble in understanding the working of sequence endsequence in system verilog. Please explain me about the sequence part. What is that ## operator meant for? and what if i change the values???
Thanks in advance...
module sequence_test();
reg a,b,c;
reg clk = 0;
sequence abc;
@(posedge clk) a ##1 b ##1 c;
endsequence
always @ (posedge clk)
begin
@ (abc) $display ("@%g ABC all are asserted", $time);
end
initial begin
$monitor("@%g clk %b a %b b %b c %b", $time, clk, a, b, c);
repeat (2) begin
#2 a = 1;
#2 b = 1;
#2 c = 1;
#2 a = 0;
b = 0;
c = 0;
end
#2 $finish;
end
always #1 clk = ~clk;
endmodule
Last edited: