Separation in non overlapping clock

[pankajpc]

Hi Fellas,

I had a question regarding non overlapping clock. How do you decide the separation between non overlapping clock for negative charge pump design for cmos image sensor pixel transfer gate. The separation between the clocks can be 1ns, 2ns, 5ns etc. How do you fix the separation for the non overlapping clocks. Some of the things that can be affected are power dissipation, settling time, voltage level , etc.

thanks

 

[dick_freebird]

Look at the RC tails of your switched nodes, and decide how much error (sig proc) or charge (power) residue you can stand to leave behind.

 

[crutschow]

How do you decide the separation between non overlapping clock

It's mostly related to tolerances.
The separation should be sufficient so that there is still no overlap for worst-case time rise-time and signal delays.