Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
VDD for IO have large current surge such that it is more noisy, and probably have a large SSO (Simultaneousely Switching noise) as compared to digital core.
so to prevent false trigger (e.g. large ground bounce) of digital core, usually they are separated,
basically, IO pad (for real IC) contained ESD protection circuit which must handle very large current. So, if we use same VDD for IO pad and the core circuit, there are possibility that the huge current (during electrostatic spike) can damage the core circuit.
VDD for IO have large current surge such that it is more noisy, and probably have a large SSO (Simultaneousely Switching noise) as compared to digital core.
so to prevent false trigger (e.g. large ground bounce) of digital core, usually they are separated,
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
