quyleanh
Member level 3
My layout has 6 termials NMOS: D, G, S, B, DNW_ISO, PSUB.
B is connected to VSS
DNW_ISO (deep nwell isolation) is connected to VDD
PSUB is connected to VSSPS
I can isolate the local PWELL (B termial) and the PSUB (PSUB) terminal by adding DNW.
Because the layout is standard cell so I cannot surround DNW layer by NWELL ring (which is should be done in that way). If I add NWELL ring, I will not abut with the other cell.
Because the DNW layer is not surrounded by NWELL ring, LVS check notify the Softcheck error, which is PWELL and PSUB is shorted.
Could anyone tell me how can I separate local PWELL and PSUB to pass LVS softcheck in this case? Thank you.
B is connected to VSS
DNW_ISO (deep nwell isolation) is connected to VDD
PSUB is connected to VSSPS
I can isolate the local PWELL (B termial) and the PSUB (PSUB) terminal by adding DNW.
Because the layout is standard cell so I cannot surround DNW layer by NWELL ring (which is should be done in that way). If I add NWELL ring, I will not abut with the other cell.
Because the DNW layer is not surrounded by NWELL ring, LVS check notify the Softcheck error, which is PWELL and PSUB is shorted.
Could anyone tell me how can I separate local PWELL and PSUB to pass LVS softcheck in this case? Thank you.