Hello everyone.
I am a graduate student working on a CMOS photo sensor (PGSPAD). My sensor is almost similar to a CMOS MOSFET. My question is,
I want to plot drain voltage vs drain current at different gate voltages. But I am confused about which one to use for the drain voltage "innerVoltage" or "OuterVoltage"? And what is the difference between the "innerVoltage" and "OuterVoltage"?
It might be the "core device" vs that plus the "access resistance" (probe resistance, contact resistance, cabling).
A second question is whether certain elements of a FET like ohmic S/D regions, LDD or LDMOS drift region (which nohow deserves bundles into a classic symmetric MOS model, acting more as a cascoded JFET in series with the drain, gate is body). That, I haven't the TCAD experience so say.