Saransh22
Newbie level 5
I have designed analog circuit on cadence following SENT datasheet and it is working well as with the given data and is been received,
but now As SENT uses CRC and tick-generator So if I design these blocks using Verilog and generate layout but where am I suppose to put them
I didn't able to find a proper reference for the block diagram or architecture of SENT protocol.
I need your suggestion on this Thank you.
but now As SENT uses CRC and tick-generator So if I design these blocks using Verilog and generate layout but where am I suppose to put them
I didn't able to find a proper reference for the block diagram or architecture of SENT protocol.
I need your suggestion on this Thank you.