Sending data from PC to FPGA via Ethernet

[mrflibble]

... Then how to distinguish the packet is coming from GEN component or from PC (netcat)??

Usually by inspecting the packet. Assuming you made your packets identifiable in some way. Anyways, I strongly suspect the answer will be "what design?" What question? This one: "Do you have an actual design you are trying to implement? Or are you just slapping networkey things together and see how it goes?" If you do have a plan, could you describe it?

 

[beginner_EDA]

"Do you have an actual design you are trying to implement? Or are you just slapping networkey things together and see how it goes?" If you do have a plan, could you describe it?

Hi,
I have specific/actual design. I am implementing following design:

**broken link removed**

The block diagram of major components of this design is in attachment.
on receiving side, UDP Port to Channel Mapper (UCM) component of this block diagram has following information:

Destination UDP Port = must match user programmed value (in verilog design code)

its corresponding c code for setting register say:

int map_udp_port_to_channel(void *base, alt_u32 channel, alt_u16 udp_port_number) {
    
    alt_u32 channel_reg;
    
    // is the channel already enabled?
    switch(channel) {
    case(0):
        channel_reg = UDP_PORT_MAPPER_RD_CHAN_0_PORT(base);
        break;
    case(1):
        channel_reg = UDP_PORT_MAPPER_RD_CHAN_1_PORT(base);
        break;
    case(2):
        channel_reg = UDP_PORT_MAPPER_RD_CHAN_2_PORT(base);
        break;
    case(3):
        channel_reg = UDP_PORT_MAPPER_RD_CHAN_3_PORT(base);
        break;
    default:
        return 1;
    }
    
    if(channel_reg & UDP_PORT_MAPPER_CHAN_X_EN_MASK) {
        return 2;
    }
    
    // not already enabled, then we enable it with the input port number
    channel_reg = udp_port_number & UDP_PORT_MAPPER_CHAN_X_PORT_MASK;
    channel_reg |= UDP_PORT_MAPPER_CHAN_X_EN_MASK;
    switch(channel) {
    case(0):
        UDP_PORT_MAPPER_WR_CHAN_0_PORT(base, channel_reg);
        break;
    case(1):
        UDP_PORT_MAPPER_WR_CHAN_1_PORT(base, channel_reg);
        break;
    case(2):
        UDP_PORT_MAPPER_WR_CHAN_2_PORT(base, channel_reg);
        break;
    case(3):
        UDP_PORT_MAPPER_WR_CHAN_3_PORT(base, channel_reg);
        break;
    default:
        return 1;
    }
    
    return 0;
}

So, I guess if I set here in c code specific port number for UDP packet and assign it to one of the channel and then use this port number while sending packet from PC(netcat) to FPGA, then I might receive these packet (without header) at Avalon source interface of UDP payload Extractor (EXT) component of corresponding channel. Any suggestion please.