Send a clock out along with data

[Qwerty112233]

Hi,

For IPs that send out clock along with data like SPI, XSPI

How do you send the clock out (what cts constraint or timing constraint) to make sure it works on the receiving side? I realize if the outgoing clock will be used to clock flops on the receiving block, and if i dont build it to the right spec it could have crazy delays on the clock path and cause hold/setup problems ?

So far i have only dealt with virtual clocks to constrain my data IP and OP ports, but i havent given much thought to sending output CLOCKS..and how to build these in a way that works on the receiving side..

Do I need special commands on the clk output port? Or related data ports that are to be timed with this clk output port? Currently i have the data OP ports constrained to a Virtual clock that mimics the waverform on the clock output port.

 

[KlausST]

Hi,

I guess the DATA goes through a DFF with ENA, do the same with the interface CLK.

This is the usual way for SPI or similar.
For sure there may be interfaces where this method is notu suitable.

It all depends on the specification/requirements.

If you want to discuss further you should post some realistic specifications and a sketch.

Klaus

 

[D.A.(Tony)Stewart]

The cable quality, length and clock recovery speed and quality are interdependent tradeoffs.

clock+recovery+xspi - Google Search

 

[kaz1]

Hi,

For IPs that send out clock along with data like SPI, XSPI

How do you send the clock out (what cts constraint or timing constraint) to make sure it works on the receiving side? I realize if the outgoing clock will be used to clock flops on the receiving block, and if i dont build it to the right spec it could have crazy delays on the clock path and cause hold/setup problems ?

So far i have only dealt with virtual clocks to constrain my data IP and OP ports, but i havent given much thought to sending output CLOCKS..and how to build these in a way that works on the receiving side..

Do I need special commands on the clk output port? Or related data ports that are to be timed with this clk output port? Currently i have the data OP ports constrained to a Virtual clock that mimics the waverform on the clock output port.

This reply applies to FPGA but I guess same applies to ASIC

outputs are constrained based on delay command, as per my example:
set_output_delay –clock clkA –max 2 [get_ports dout[*]]
set_output_delay –clock clkA –min -1 [get_ports dout[*]]

You need to identify a name for your clock & determine delay values.
Delay values depend on what info you have about external device for example
if you are given setup, hold of external device then:

max = TSU + (max data board delay - min clock board delay)
min = – TH + (min data board delay - max clock board delay)

What you describe is "Source Synchronous io".
so you can ignore the board terms if data and clock are hand-in-hand so in short:

max = TSU
min = -TH

 

[FvM]

Are we talking about high speed interfaces (>= 50 MHz fclk)? Otherwise there's probably no need for specific timing constraints because standard SPI has 0.5/fclk setup and hold margin.

 

[kaz1]

Are we talking about high speed interfaces (>= 50 MHz fclk)? Otherwise there's probably no need for specific timing constraints because standard SPI has 0.5/fclk setup and hold margin.

If external device has 0.5 setup/hold then put that in the output delay formula that I mentioned to center align the offset between data and its clock.

If external device has some automatic control of timing then no constraints are needed but still for sake of constraining we can add it.

if an ip is taking control of this offset at asic then thanks.

if no one then anchor & hope + prayer as speed could be too slow.

 

[dpaul]

@Qwerty112233 ,
I work with FPGAs and will answer accordingly. You should have mentioned if your requirement is for ASIC or FPGA.

Do I need special commands on the clk output port? Or related data ports that are to be timed with this clk output port?

Nevertheless, it is easier and better to constrain the related data ports associated with the SPI clock. In FPGAs I would just use an ODDR to o/p the clock to the FPGA pin. I would put no constrain on it (so no meddling around with clock skews).
But I would use the set_output_delay or set_input_delay constrains on the data ports such that SPI timing relationships are not violated.
Yes some engineers might call this cheating, but who cares if data can be exchanged correctly all the time!

 

[KlausST]

Hi,

Do I need special commands on the clk output port?

Form the ASIC/FPGA side this generated CLK is not a dedicated clock and thus is not treated this way.
A generated SPI_CLK is treated like any other generated signal (like MOSI for example).

Klaus

 

[kaz1]

Hi,


Form the ASIC/FPGA side this generated CLK is not a dedicated clock and thus is not treated this way.
A generated SPI_CLK is treated like any other generated signal (like MOSI for example).

Klaus

That is possible alternative. Clock would be Q output as data from an io register. In this case it might be ok to set as generated clock, edge aligned (I am not sure)
The ideal is that it is related to a base clock as below:

 

[KlausST]

Hi,
@kaz1:

if I´m not mistaken...
this shows a continous clock interface.

But SPI (OP mentioned in post#1) isn´t a continous clock interface.

Klaus

 

[kaz1]

Hi,
@kaz1:

if I´m not mistaken...
this shows a continous clock interface.

But SPI (OP mentioned in post#1) isn´t a continous clock interface.

Klaus

Yes just realised that this is a slow bursty interface, common with embedded software. The data/sclk relationship is dictated by the standards and has more than configuration.
clock would have to be Q output just like data. The two devices have to agree on clock phase. So this behavior have to be mapped to sdc commands though the io logic can control it but both data and sclk must have same delay to pins.

https://www.analog.com/en/analog-dialogue/articles/introduction-to-spi-interface.html

 

[Qwerty112233]

Thanks guys, loads of stuff here to process and understand for me.

I will try to use sclk_out as a data OP port in constaints.

On the multi master mode, I have a confusion. I see mi and SS (chip selects??) being timed to SCLK for clock gating hold check..and since it's a AND gate i see the period requirement is +0.5 of the SCLK at the and gate pin. Is this even a real path i need to worry about?

Referring to the AND gate circuitry on the left..

 

[KlausST]

Hi,

You need pull ups at each bus line to get HIGH on DISABLED.

And while it´s agood idea to start only when the bus is free .. it does not prevent from two masters accessing the bus at the same time.
Thus you need to limit short circuit currents.

Klaus

 

[FvM]

SPI protocol standard has no provisions for multi-controller ("multi-master") operation. JEDEC XSPI (JESD251) even states single controller operation explicitely in topology description. Some controllers, e.g. STM32 SPI have vendor specific features for multi-controller operation, but they don't rely on an agreed standard and therefore are in case of doubt unable to interoperate with controllers of other vendors..