self-verifying test bench for HDL based desingns

[graphene]

I would like to know about self-verifying test bench for verifying HDL based designs (either Verilog or VHDL). I know that we usually, manually define the test stimilus but I was asked to come out with a self-verifying (Selbstprüfende in German)test bench. Can someone share your idea? thanks in advance.

 

[ads-ee]

A self verifying testbench is one that will generate data send it to the UUT, then captures the UUT output and check if the output data is correct. The whole purpose of this type of testbench is that you can easily regression the design when you make changes and you won't have to resort to visual inspection of simulation waveforms to determine if the design is still working.

 

[graphene]

thank you ads-ee.. now, I understand the purpose... on that note I would also like to know if it needs a aditional learning to design such a test bench or how do I get started with it...

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I would like to see one such simple test bench... can someone help me...
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PS: I googled before asking here, just that, I am not clear as in what to look for !!

 

[ads-ee]

For SystemVerilog look for OVM, UVM.
https://www.accellera.org/downloads/standards/uvm

Mentor has a website (https://verificationacademy.com/) devoted to training engineers on using UVM, though you may have difficulty signing up on the site if you don't have a corporate email account. Don't get discouraged though, when you see how much information there is.

regards

 

[layowblue]

another useful link:
http://www.testbench.in/