self triggered and non-self triggered always block

Please can some body explain me difference between these 2 always block execution.

---- Non-Self Triggered ------
module osc1 (clk);
output clk;
reg clk;
initial #10 clk = 0;
always @(clk) #10 clk = ~clk;
endmodule
----------------------------------------

------- Self Triggered ------
module osc2 (clk);
output clk;
reg clk;
initial #10 clk = 0;
always @(clk) #10 clk <= ~clk;
endmodule
----------------------------------------

An always block is just a looping construct. Initial or always blocks do not trigger, they are processes that wait for delays or events to occur.
From a simulation perspective

always statement
is the same as
initial forever statement

and statement can be wrapped with

begin
statement
end

So we can re-write your always block as

The way to read the code representing the always block is as follows:

1. Start a process.
2. enter a loop
3. wait for clk to change (the first time will be at time 10 when it goes from X to 0.
4. then wait 10 units
5. Assign clk at the end of the current delta time slot with the value ~clk. Do not block waiting for the assignment to complete
6. go back to the top of the loop

Since you use a non-blocking assignment <=, the process will be blocked waiting for a change when the assignment to clk changes.
In the the case where you use a blocking assignment = , the assignment to clk complete, meaning the clk changes before the loop goes back to the @clk. So that's why it appears not to trigger again.

With blocking how is this working I mean self triggered ?

module tb (clk);
output clk;
reg clk;
initial #10 clk = 0;
always #10 clk = ~clk;
endmodule

Please can some body point me to the book where I can read verilog execution semantics.
Thanks

Hi!

Well, the reason why the first of the examples you provided does not work (i.e., it does not generate any clock waveform) is because of how blocking assignments are treated in Verilog. In general, you might consider blocking assignments as a single-phase process, while non-blocking ones as two-steps process. This means that the RHS of a blocking assignment will be actually assigned to the LHS once it is evaluated; with non-blocking assignments, on the other hand, the RHS is evaluated at the beginning of a time period, while it will be actually assigned at the end of it. To understand the way it works, consider the following "simulation":

- at time 0 (when you start simulation), clk will be assigned 0 (i.e., it is initialized from low). Actually, this happens at +10, since in the initial block you are specifying a delay, but this doesn't matter, since it is just a +10 shift along the time axis. In the meanwhile, you enter the always block (at the first time), and schedule an event at +10 to invert the clk signal. This is a blocking assignment, so it is "atomic"

- at time 10- you check events in the queue: Verilog will find an always block to be evaluated IF AND ONLY IF the signal in the sensitivity list changes, i.e. iff the signal clk is to be changed at that moment (10-). However, use previously used blocking assignment, so Verilog doesn't see any real assignment to be done at 10-, since it is already performed, thus the always block will not schedule any additional event! clk will remain 1 until the end of the simulation

In case you use non-blocking assignment, on the other hand: at time 0, you evaluate RHS of the non-blocking assignment, and wait until 10- to effectively update the value of the clk signal. In the meanwhile, at 10-, Verilog analyses the always instruction and sees that it is active if clk changes, AND it sees that clk is to be changed still (since it is a non-blocking assignment), so it enters the always block and will schedule it again after +10 time units. At the end you will have a cycle waveform.

Hope this helps, but in any case, you can start reading the following paper:

**broken link removed**

it provides a lot of examples (still, it is quite hard to understand it fully).