selection of clock duty cycle

[madmax]

abel 25% duty cycle clock

Hi ,

I have to transfer a data from Flip flop1 to Flip flop2,Flip flop's hold time is '0' and clk to q delay is 'x' ns.Between Flip flops there are combinational logics which takes 'y' ns.I'm having a pulse whose high period is more than 'x' ns.Its duty cyle is 20% high and 80% low.Can I use this pulse or is there any need that I have to use a clock having dutycycle of 30% or 40% or 50% high and 70% or 60% or 50 % low.Assume both the frequency of the clock and pulse are same.Is there any notes which says about the duty cycles selection of a clock.

Thanks in advance ,

Max

 

[elektrom]

duty cycle

I don't understand your design (MHz?, Buit-in ram?, FPGA?, ASIC?) but, basically, If all of flip flop is clocking with the same edge (rising-edge/falling-edge), No need to worry about duty cycle. In my opinion, duty cycle should be around 25~75%. 20% may not good enough.

 

[Pim]

Re: duty cycle

Not having seen your design, nor fully understanding your description of it I can not give you a perfect advise. However, in general the question of duty cycle is not the main issue, but the time that signals must be held stable on the flip-flop's inputs prior to the triggering signal (the clock signal). Also, you must not forget to check out what the worst-case times are. In addition, do not forget that flip-flop's are sometimes sensitive to dips and spikes on the power supply as well as interference (in case you for example wire-wrap the design and use CMOS and long wires for the input signals -> will be capacitively and inductively coupled to nearby wires and having high input impedance of the CMOS inputs means caution).

/Pim

Hi ,

I have to transfer a data from Flip flop1 to Flip flop2,Flip flop's hold time is '0' and clk to q delay is 'x' ns.Between Flip flops there are combinational logics which takes 'y' ns.I'm having a pulse whose high period is more than 'x' ns.Its duty cyle is 20% high and 80% low.Can I use this pulse or is there any need that I have to use a clock having dutycycle of 30% or 40% or 50% high and 70% or 60% or 50 % low.Assume both the frequency of the clock and pulse are same.Is there any notes which says about the duty cycles selection of a clock.

Thanks in advance ,

Max

 

[madmax]

Hi ,

If my flip flop is able to produce the output within the pulse period then can i use a pulse instead of a clock ,if all my flip flops are working in rising edge.

thanx in advance ,

max

 

[jiang]

Hi ,

If my flip flop is able to produce the output within the pulse period then can i use a pulse instead of a clock ,if all my flip flops are working in rising edge.

thanx in advance ,

max

is your design in physical phase? do you have experience with clock tree layout?
if not, using gating clock in your design is a worst choice.
using gating clock, you must take care more in physical design.

 

[madmax]

Thank you jiang

I'm using FPGA so I think no need to care about physical layout.So for FPGA can I use a pulse mentioned having the above mentioned conditions.

 

[FNK]

I think the best way to verify is to do timing simulation with your defined clock. This way it will get clear if it will work or not.

 

[elektrom]

duty cycle

Hi ,

If my flip flop is able to produce the output within the pulse period then can i use a pulse instead of a clock ,if all my flip flops are working in rising edge.

thanx in advance ,

max

The answer is possible. But!!. Try to feed this output to global clock buffer in FPGA and use its output signal as a global clock for all flip flops.
Without global clock buffer, It's easy to face with clock skew problem.

PS. You may have to instanciate a global clock buffer by hand.