seeking help in writing the synthesizable "for loop" code in verilog

ranga4a2 · Jan 17, 2012

hi everybody,
code:

reg [0:250]primset[0:200];
input p;
integer i;

for(i=1;i<p-1;i=i+1)
begin
primset;=i;
end

while i am writing this for loop in xilinx. i am getting this error "For loop stop condition should depend on loop variable or be static".

can any one help me in solving this error.

j_andr · Jan 17, 2012

the example itself doesn't make sense, but you can solve
the problem this way:

Code:

localparam max = 201;

reg [x:0] primset[0:max-1];

integer i;

 always @(posedge clk)
    for( i=0; i<max; i=i+1 )
      if ( i<p )      primset[i] <= i;
      else            primset[i] <= primset[i];

J.A

guitarguy12387 · Jan 18, 2012

Loops get unrolled in synthesis and are implemented as parallel hardware. They are not used the same way you would use them in software. They are used to generate multiple instances of a circuit. Therefore, the bounds on the loop must be known at 'build time'.

permute · Jan 18, 2012

yes, you would need to do the loop over the maximum length, and then add an "if loopvar < inputvar".

seeking help in writing the synthesizable "for loop" code in verilog

ranga4a2

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j_andr

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permute

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seeking help in writing the synthesizable "for loop" code in verilog

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