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| void UARTSend(uint32_t portNum, uint8_t *BufferPtr, uint32_t Length)
{
while ( Length != 0 )
{
if ( portNum == 0 )
{
/* THRE status, contain valid data */
#if !TX_INTERRUPT
while ( !(LPC_UART0->LSR & LSR_THRE) );
LPC_UART0->THR = *BufferPtr;
#else
/* Below flag is set inside the interrupt handler when THRE occurs. */
while ( !(UARTTxEmpty0 & 0x01) );
LPC_UART0->THR = *BufferPtr;
UARTTxEmpty0 = 0; /* not empty in the THR until it shifts out */
#endif
}
else
{
/* THRE status, contain valid data */
#if !TX_INTERRUPT
while ( !(LPC_UART1->LSR & LSR_THRE) );
LPC_UART1->THR = *BufferPtr;
#else
/* Below flag is set inside the interrupt handler when THRE occurs. */
while ( !(UARTTxEmpty1 & 0x01) );
LPC_UART1->THR = *BufferPtr;
UARTTxEmpty1 = 0; /* not empty in the THR until it shifts out */
#endif
}
BufferPtr++;
Length--;
}
return;
}
void UARTInit(uint32_t portNum, uint32_t baudrate)
{
uint32_t i, Fdiv;
uint32_t regVal;
if ( portNum == 0 )
{
UARTTxEmpty0 = 1;
UARTCount0 = 0;
for ( i = 0; i < BUFFSIZE; i++ )
{
UARTBuffer0[i] = 0;
}
NVIC_DisableIRQ(UART0_IRQn);
SetupUART_Location( portNum, 0 ); /* default is location 0 */
/* Enable UART 0 clock */
LPC_SYSCON->PRESETCTRL |= (0x1<<2);
LPC_SYSCON->SYSAHBCLKCTRL |= (0x1<<12);
LPC_SYSCON->UART0CLKDIV = 0x1; /* divided by 1 */
LPC_UART0->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
regVal = LPC_SYSCON->UART0CLKDIV;
Fdiv = ((SystemCoreClock/regVal)/16)/baudrate ; /*baud rate */
LPC_UART0->DLM = 0x00;
LPC_UART0->DLL = 0x13;
LPC_UART0->LCR = 0x03; /* DLAB = 0 */
LPC_UART0->FDR = 0x10; /* set to default value: 0x10 *///0x10
LPC_UART0->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
/* Read to clear the line status. */
regVal = LPC_UART0->LSR;
/* Ensure a clean start, no data in either TX or RX FIFO. */
while ( (LPC_UART0->LSR & (LSR_THRE|LSR_TEMT)) != (LSR_THRE|LSR_TEMT) );
while ( LPC_UART0->LSR & LSR_RDR )
{
regVal = LPC_UART0->RBR; /* Dump data from RX FIFO */
}
/* Enable the UART Interrupt */
NVIC_EnableIRQ(UART0_IRQn);
#if TX_INTERRUPT
LPC_UART0->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART interrupt */
#else
LPC_UART0->IER = IER_RBR | IER_RLS; /* Enable UART interrupt */
#endif
}
else
{
UARTTxEmpty1 = 1;
UARTCount1 = 0;
for ( i = 0; i < BUFFSIZE; i++ )
{
UARTBuffer1[i] = 0;
}
NVIC_DisableIRQ(UART1_IRQn);
SetupUART_Location( portNum, 0 ); /* default is location 0 */
/* Enable UART 1 clock */
LPC_SYSCON->PRESETCTRL |= (0x1<<3);
LPC_SYSCON->SYSAHBCLKCTRL |= (0x1<<13);
LPC_SYSCON->UART1CLKDIV = 0x1; /* divided by 1 */
LPC_UART1->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
regVal = LPC_SYSCON->UART1CLKDIV;
Fdiv = ((SystemCoreClock/regVal)/12)/baudrate ; /*baud rate */
//LPC_UART1->DLM = Fdiv / 256;
//LPC_UART1->DLL = Fdiv % 256;
LPC_UART0->DLM = 0x00;
//LPC_UART0->DLL = Fdiv % 256;
LPC_UART0->DLL = 0x13;
LPC_UART1->LCR = 0x03; /* DLAB = 0 */
LPC_UART1->FDR = 0x10; /* set to default value: 0x10 */
LPC_UART1->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
/* Read to clear the line status. */
regVal = LPC_UART1->LSR;
/* Ensure a clean start, no data in either TX or RX FIFO. */
while ( (LPC_UART1->LSR & (LSR_THRE|LSR_TEMT)) != (LSR_THRE|LSR_TEMT) );
while ( LPC_UART1->LSR & LSR_RDR )
{
regVal = LPC_UART1->RBR; /* Dump data from RX FIFO */
}
/* Enable the UART Interrupt */
NVIC_EnableIRQ(UART1_IRQn);
#if TX_INTERRUPT
LPC_UART1->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART interrupt */
#else
LPC_UART1->IER = IER_RBR | IER_RLS; /* Enable UART interrupt */
#endif
}
return;
}
int main (void)
{
SetupUART_Location(0,0);
UARTInit(0,9600);
while(1)
{
LPC_UART0->IER = IER_THRE | IER_RLS;
UARTSend( 0, "K" , 1);
LPC_UART0->IER = IER_THRE | IER_RLS | IER_RBR;
}
} |