You might want to look there
Yes, as I said, I've seen it. I guessed the "substrate" text at the case connection is a typo. Please notice also my more detailed considerations about expectable differences between original Siliconix and second source Valvo/Philips 2N4220.
As most substrates are connected to gate or source, it is unnecessary to specify any special ratings.
With JFET, they are alway connected to the gate, I think. My statement clearly applies to the 4-pin devices, e.g. 2N4220.
If the fourth pin would be a separate substrate connection,
then it must have a maximum rating.
I reviewed my literature about JFET chip design and found, that you are basically right about the principle shape of the gate construction. Thank you for clarifying this point.
The same literature also shows, how both gates (bottom G2 and top G1) are usually shorted to each other, by simply extending the top gate diffussion length. So I still wonder if there will be any reference for a JFET with separate substrate electrode?
For reference, I add two pages from the said literature (in German: Das FET Kochbuch, Texas Instruments Deutschland, 1977).