Seal Ring DRC error

Dear friends

I have some issues with the seal-ring design.

We are working on XFAB XH035 µm technology.

We have installed the seal ring Pcell by following the steps from "User Guide Implementation of
Peripheral Ring – Design kit in Cadence".

The Pcell is successfully added to Cadence and also we confirmed the structure by analyzing the cell with respect to the seal ring design rules given by "Design Rule Overview XH035 –Multi-Project Designs Document DR_SR_XH035 Release 1.2.0"

After surrounding our prototype chip with the seal ring we received numerous DRC errors,

On our way to investigate the reason we have created a new layout cell and only inserting the seal-ring Pcell and by running DRC over it the same amount of errors are generated. It looks to us that Pcell itself is not DRC clean as it is supposed. Also, it looks that DRC is confusing between the seal type metals and the metal draw-type used in the technology.

I have taken a snapshot of the DRC error and attached it to the email.

We are also thinking that we might not need to run the DRC over the seal ring.

The last issue is relevant as well since we want to connect the seal ring to the chip ground PAD, the metals used in the chip core and PAD are type "draw", for example, MET draw, while for the ring is type seal. How to connect between them.

I am are looking forward to your kind help

Best Regards

Many foundries want to place the seal / scribe structure themself and if the scribe is provided it's for fitment and not expected to be part of what's taped out to them (hence on the hook for clean DRC).

If the scribe were a DRC target it might use alt layers to steer rules appropriately for both scribe content and scribe:core rules. Or there might be an adjunct layer whose presence invoked / suppresses scribe related or scribe-bothered rules. Might inquire of the foundry design support contact, about how or whether a seal-inclusive layout is expected to pass DRC, and if so, steps.

Your Seal Ring seems very small. You should scale it regarding to chip size.
It cannot be smaller than certain size. Errors are concerned with it.

Dear Friends,

Thank you very much for your help, I have contacted the company and they replied that it is better to the seal ring themselves as also mentioned by freebird, so I will leave this step for them,

However, just to make it useful for the any reader come to see this post, I have found the reason why I am getting DRC errors,
Since I am using the standard Assura setup for the core chip design, this setting will not identify the seal ring data type, for example, MET1 type is "drawing" for the standard core while the layers of the seal ring are with "seal" data type.

If you insist on doing the seal ring yourself, then you have to work with PVS tool after installing the necessary seal ring data to your design kit.

Regards