SDRAM routing guidelines

[pcb87]

Hi all,

I am working with a pcb with 4 SDRAM chips (TSSOP package) .Data, address ,control and and clock are connected to all the 4 SDRAM chips. What is the routing strategy that i should follow.What should be the length of the signals.


Thanks in advance

 

[marce]

What does the device data sheet say?

 

[pcb87]

Hi marce,

Datasheet doesnt specifies anything about routing guidelines. I have done pcb's with DDR SDRAMs . I think SDRAM s are not that critical as DDRs. Do i need to follow the same guidelines for DDR.

 

[kabaleevisu]

Hi PCB87,
First,Group the signal (address,data and control signal) like For Address (0-7 signal with BA0 and BA1) for Data signal (0-7) with DQ signal.Route the DQ signal first after that route the data signal.set the min and max in tool let me know which tool r u using

 

[pcb87]

Hi PCB87,
First,Group the signal (address,data and control signal) like For Address (0-7 signal with BA0 and BA1) for Data signal (0-7) with DQ signal.Route the DQ signal first after that route the data signal.set the min and max in tool let me know which tool r u using

Hi Kapil,

I am using Cadence allegro. Memory chip am using is SDRAM not DDR .It doesnt have the data strobe, there's only data and mask signals.There are 4 SDRAM chips.

 

[kabaleevisu]

please post the datasheet

 

[pcb87]

please post the datasheet

Hi Kapil,

Datasheet is attached.

 

[kabaleevisu]

Hi,
First group the signal address and data signal Address (Addr0-12) data BUS 1(Data0-7 and DM0,DQS0) Data Bus2 (8-15 with DM1 and DQS1)and control signal (CAS,CS0,CS1,RAS,WE,BA0,BA1) set in constraint Manager

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after that route the signal for data signal reference length is strobe signal you have match the length matching according to the data strobe.

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for your reference follow this https://www.edaboard.com/threads/283545/#post1307462
it may be helpful for you

 

[pcb87]

Hi Kapil ,

Thanks for that, But i have a few doubts.
What should be the minimum length of the data signals and address signals?
Is the clock length greater than data sig?
Do i need to route address ,data and control sig in same length.

Can u post the placement of DDR in any of your pcbs?


Thanks in advance

 

[kabaleevisu]

hi still i am not familiar in DDR better post your placement i will try to help