onuurkse
Newbie
Hi guys, I'm working with the IS42S16400 model 64-Mbit SDRAM that I have. I write 16-bit data to random addresses and read. It's okay to write, but I'm having trouble on the reading side. I used the SDRAM controller model in the link. The friend who designed it used IS42S16160G. I changed the timing and address sizes according to my own integration.
constant CL : integer := 2;
constant tRCD : integer := 2;
constant tRP : integer := 2;
constant tRAS : integer := 4;
constant tRC : integer := 7;
constant tREF : integer := 64;
In the test program I designed, I printed the values I specified in the addresses below and then had them read.
Address -> Value
1024 -> 3000 + state
2097152 -> 16000 + state
2048 -> 12000 + state
8192 -> 6800 + state
16384 -> 1800 + state
32768 -> 5862 + state
As seen in the picture, the data I wrote was read correctly.
However, if I change any address or address content and read, the address content is read incorrectly. I changed the address content of 2097152 to 19000. He read this address correctly, but read 1024 as 1814.
Sometimes it reads incorrectly on the first load. Why is it reading incorrectly this way?
SDRAM: https://bertantaskin.com/fpga-ile-sdr-sdram-kontrolu/
SDRAM Test: https://github.com/onur94/FPGA/blob/master/SDRAM_Controller_Fifo.vhd
constant CL : integer := 2;
constant tRCD : integer := 2;
constant tRP : integer := 2;
constant tRAS : integer := 4;
constant tRC : integer := 7;
constant tREF : integer := 64;
In the test program I designed, I printed the values I specified in the addresses below and then had them read.
Address -> Value
1024 -> 3000 + state
2097152 -> 16000 + state
2048 -> 12000 + state
8192 -> 6800 + state
16384 -> 1800 + state
32768 -> 5862 + state
As seen in the picture, the data I wrote was read correctly.
However, if I change any address or address content and read, the address content is read incorrectly. I changed the address content of 2097152 to 19000. He read this address correctly, but read 1024 as 1814.
Sometimes it reads incorrectly on the first load. Why is it reading incorrectly this way?
SDRAM: https://bertantaskin.com/fpga-ile-sdr-sdram-kontrolu/
SDRAM Test: https://github.com/onur94/FPGA/blob/master/SDRAM_Controller_Fifo.vhd