SDF file cannot find the lower level instance!

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yuanqi

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Hi, I have a top level module with its .sdf file. But when I want to simulate the system, I got lots of errors saying "Failed to find INSTANCE xxxxx" which are all lower level instances in sub-modules? Any ideas about it? Thanks a lot!
 

First, search the instance in the sdf.
If it exists, one of the likely reasons is escaping or not escaping the special charactors such as slashes, square brackets etc. You need to match them to the ones in the netlist in that case.
 

I could find all the instance in netlist file in the sdf file, and check the space, square as well.
One thing I'm thinking about is still the hierarchical problem, as the lower level instance cannot be found...
 
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So, does your sdf have hierachical delimiters escaped or not ?
If it is escaped, is it done in the way to match the netlist's.
If it's not escaped, is it not supposed to be escaped ?
Is the design flat or fully hierarchical or partially hierarchical ?

In most of the time the sdf has an issue with simulation or STA, it's about a escape sequence of special characters that didn't match the netlist's.

Frankly, I don't see enough information to analyze the issue from your post and we cannot help much.
 
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YES! You are right, the RTL complier has added a backslash at the beginning of some instances. I think it's due to incompatibility between the synthesizer and VHDL code, I think I could avoid it by writing Verilog. Thanks a lot
 

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