Sdf back annotation in a systemverilog design with interfaces

[arash1902]

Hi all, I have a DUT which is encrypted netlist and .sdf file (normally we do functional and timing simulations with these inputs). I used interface feature in SystemVerilog so I don't define any port for the modules. here is part of the

module topmodule(
   intf1	clk,inp1,inp2,outp);
   intf1  out();
  // Instance the interface with an input, using named connection
	 RC DUT(clk, inp1, inp2, out);

and here is part of interface definition,

interface intf1;

	logic data=0;

and I have two task and function in my interface. I write a SDF file but modelsim said 'failed to find port '/tbench_top/clk/data' and 'failed to find port '/tbench_top/DUT/inp1/data'.
It means it didn't recognize the 'data' port which is defined within the interface.
here is part of my SDF file,

INTERCONNECT clk.data DUT.inp1.data (.145::.145) (.125::.125))

So, how must I write SDF when I use interfaces?
Thanks for any help.