SDC constraints for MUXed clock input + clock divider + MUXed clock output

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shlooky

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Hi there,

I am trying to write SDC contraints for given design...
Input clocks are defined by "create_clock" commands (not shown in the picture).
MUXes are covered by "set_clock_groups" commands.
Freq_div outputs should be covered by "create_generated_clock" commands.

I am not 100% sure about the pin definitions, could you guys please check it?

Am I missing something?
Any advice maybe?

Thanks in advance...

 
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Hi,

Thanks for the reply. The tool is fine with the definitions
I am more concerned about the timing results based on SDC / correct constraining of muxed input and output.

See, I am not familiar with muxed clock designs at all and the picture/SDC commands are just what I've gathered online, but there are conflicting (and confusing) answers so I wanted more experienced designer to look at it and maybe clear things up.

Shlooky
 
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why not just defining:
1. a clock network from mux_in.Z and stop to mux.out input pins to equilibrate the flop inside the divider.
2. a clock network from mux_out.Z, to equilibrate the remaining design.

OR

transform the FREQ_DIV to generate a clock enable signal with will acts on the clock gating cell, so no need of the mux_out.
 

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