SDC constraints for multiplexed clock paths

[ranaya]

Hi,

I am trying come up with proper clock constraints for a mux/div clock paths.
The design structure looks like below:

pll4x_clk is an input to the block, so that the output Tosch of the block has pll4x_clk/2, 4 and 8 options.
How to properly write the constraints in a way clocks are nicely converged ?

create_clock -name pll_out4x_clk -period 5.00 [get_ports pll_out4x_clk]

#pll4x divided by 2, 4, 8
create_generated_clock -name clk_div2 -divide_by 2 -source pll_out4x_clk [get_pins fast_div2/clk_div2]
create_generated_clock -name clk_div4 -divide_by 2 -source [get_pins fast_div2/clk_div2] [get_pins fast_div4/clk_div2]
create_generated_clock -name clk_div8 -divide_by 2 -source [get_pins fast_div4/clk_div2] [get_pins fast_div8/clk_div2]

set_clock_groups -logically_exclusive -group clk_div2 -group clk_div4 -group clk_div8

From this point onwards how to specify the multiplexed paths for Tosch ?

Thanks in advance.

 

[glennramalho]

I am not sure what you are asking for. What you did looks fine.

The important is to specify the constraints coming out of each flop. Now, the clocks will all be passed through the MUXes at the same time, so Tosch will see three clocks comming out. The logically_exclusive keeps the tool from making checks between the clock variants of the same clock so you do not get a check between div8 and div4.

Then all checks will be made using all three clocks. You then can use those clocks you generated in input delays, output delays and so on. Just remember to use the -add_delay option or when you add a constraint to a pin you will remove the previous constraint.
set_input_delay -clock clk_div4 .... somepin
set_input_delay -clock clk_div8 .... somepin -add_delay

If you need to generate a generated clock from one of these you will need to specify which is the master source as you will have multiple clocks on the same net.

I presume the root_sel[*] does not change during the operation of the PLL, right? So you can use set_disable_clock_gating_check to keep the tool from checking timing between the root_sel[*] and the clock dividers. The format is quite simple.

 

[ranaya]

I am not sure what you are asking for. What you did looks fine.

The important is to specify the constraints coming out of each flop. Now, the clocks will all be passed through the MUXes at the same time, so Tosch will see three clocks comming out. The logically_exclusive keeps the tool from making checks between the clock variants of the same clock so you do not get a check between div8 and div4.

Then all checks will be made using all three clocks. You then can use those clocks you generated in input delays, output delays and so on. Just remember to use the -add_delay option or when you add a constraint to a pin you will remove the previous constraint.
set_input_delay -clock clk_div4 .... somepin
set_input_delay -clock clk_div8 .... somepin -add_delay

If you need to generate a generated clock from one of these you will need to specify which is the master source as you will have multiple clocks on the same net.

I presume the root_sel[*] does not change during the operation of the PLL, right? So you can use set_disable_clock_gating_check to keep the tool from checking timing between the root_sel[*] and the clock dividers. The format is quite simple.

Thanks for the detailed answer, I want to create Tosch as a clock that is derived from all three mux settings.

>> If you need to generate a generated clock from one of these you will need to specify which is >> the master source as you will have multiple clocks on the same net.

This is exactly I want. But when I use -add with the generated_clock command to set up three paths to one end, genus complains about the missing master_clock. In this context what is the master clock ?

 

[glennramalho]

You don't need the extra create_generated_clock command at the output. The rule is clock paths end at a flop. They will go through other things though.
When you do create_generated_clock and add it to the output of a flop, you create a new clock on that pin. So, when you enter those three create_generated_clock commands you will have three clocks, each coming out of one of the flops. They will all propagate though the muxes and other simple logic gates, so at trost you will see all three clocks. This is the default behavior. If you want to test this you can try report_timing -from [get_clocks clockname] to each one of the three clocks and you can see that the logic clocked by trost is being checked by each of the three clocks.

Usually that is all you need. (If you are using mux-based clock dividers,where the mux is used as a logic gate to mix two different signals and generate the clock, then you would need a create_generated_clock on the output of the mux and describe what the final clock you have. This is not your case though).

Now, the -add and -master_source... That is in case you need to make more clocks from trost. Let's say you have another divider which divides clk_trost by 2. Then you would have a problem as each of the three clocks at the divider would need to be divided. So you could create three clocks at the output pin of your trost divider (which I called trostdividerout). The -add and -master_clock pins are so you can specify which is the source of each one so that the final clock has the correct propagation delay, timing, etc.

• create_generated_clock -clock trost_2by2 -source outofflopby2 -add -master_clock clk_div2 trostdividerout
• create_generated_clock -clock trost_4by2 -source outofflopby4 -add -master_clock clk_div4 trostdividerout
• create_generated_clock -clock trost_8by2 -source outofflopby8 -add -master_clock clk_div8 trostdividerout

You could also do this if you have a more complicated clock generator that can generate multiple waveforms. Let's say you have a flop that sometimes generates a 50% duty cycle, sometimes does a 25%, sometimes does something else. In that case you might want to do the -add -master to describe each clock you are generating.

You could ask if you need all these internally generated clocks. Is the fastest one enough? Well, if you just have nice posedge logic, perhaps not, but if you have a lot of flops being used as clock dividers and you often mix the clocks, for example some logic runs on clk_div2, some on trost_4by2, some on clk_div4 and so on, then you could have some odd clock reconvergence cases. Therefore, it is then best to simply try to make the SDC file to express reality as close as you can.