SDC Clock multiplexer - How to false path the "Select"

[George_P]

Hi

I have the following clk muxing structure: 4 input clocks (let's say clk1, clk2, clk3, clk4), all with the same source (clk1), 3 of them divided.

I tried defining only 1 generated clk for this structure, at the mux output (the non divided, with the max frequency). The master clock (clk1) is also defined and used as source for the generated clk.

The timing report gives timing violations in paths that go through the Select of this multiplexer. These are false paths, so I tried to false-path them. However they are still present, as if false-path is ignored (maybe you cannot false-path "through" the clock tree, but only through the datapath? If anyone knows please share your thoughts).

Any ideas:
1. How should the clock definitions be properly defined for this structure?
2. How to set the tool (e.g Primetime) to ignore paths through the "select" pin?

Thank you

 

[George_P]

Note: i know that if all clk inputs are synchronous, then the proper way would be to mux the clk-enables and not the clocks themselves. But please bear with me and assume we need to mux the clocks. Or if you prefer, assume one of the clks is asynchronous to the rest.

 

[ThisIsNotSam]

try using set_case_analysis on the select bits
I have done once this way for a chip with 7 clocks that were muxed pretty much the same way you did here. my approach worked on innovus, not sure if other tools will have the same behavior.

 

[George_P]

Thanks for the suggestion. My concern with case analysis, is that in the design we have >5 clk muxes, and some of them use as input the output of a previous mux.

So if I use case analysis for every valid combination of the muxes, I will need >30 sdc files just for functional mode. Of course this is doable, but I hope there is a more elegant way in sdc to do this.

Btw, thank you for being so helpful in this forum, I have found many useful posts/answers by you!

try using set_case_analysis on the select bits
I have done once this way for a chip with 7 clocks that were muxed pretty much the same way you did here. my approach worked on innovus, not sure if other tools will have the same behavior.

 

[ThisIsNotSam]

the SDCs would look messy, indeed. but the good thing is that the tools understand what scenarios matter and wouldn't spend time analyzing all cases separately, so it's not like you are creating 30 new corners.

 

[harpv]

Here I'm making an assumption that the false path is not really a false data path, but a false clock path.

One of the scenarios I've seen is when the master clock is generating the select signal. The tool propagates clocks through CK->Q arcs of the flop generating the selection back to master clock which becomes worst case latency.

There's an option -combinational with create_generated_clock which will only trace through combinational arcs. If your scenario is similar to what I've described having the combinational option will help.

Otherwise you could also use a clock sense to stop the clock propagation through the mux select.

 

[George_P]

Thanks,

yes, the path is as you describe it. I ended up doing this by the book:

- define one generated clock per mux input (at the mux output, and source=mux input). So 4 clks at the same definition point/pin
- use "-combinational" and "-add" for these generated clocks
- set these clocks as physically exclusive with : set_clock_groups -physically_exclusive -group clk1 -group clk2 ...

It still seems to me that an sdc structure/command for direct clk-mux definition would be useful to people.
BR

Here I'm making an assumption that the false path is not really a false data path, but a false clock path.

One of the scenarios I've seen is when the master clock is generating the select signal. The tool propagates clocks through CK->Q arcs of the flop generating the selection back to master clock which becomes worst case latency.

There's an option -combinational with create_generated_clock which will only trace through combinational arcs. If your scenario is similar to what I've described having the combinational option will help.

Otherwise you could also use a clock sense to stop the clock propagation through the mux select.