xilinx1001
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Hi,
I am trying to display different sensor readings on 7 segment in a circular sequence
I stored both the sensor readings
But I have problem while displaying the the segemnts.
I saved the sensor readings in two different arrays
Code:
Error:
Reading design: top_module.prj
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/Documents and Settings/vial1001/Desktop/New Folder (2)/Copy of s & t-8/Rs232 RefProj2/SourceFiles/RS232RefComp.vhd" in Library work.
Architecture behavioral of Entity rs232refcomp is up to date.
Compiling vhdl file "C:/Documents and Settings/vial1001/Desktop/New Folder (2)/Copy of s & t-8/project/rangesensor.vhd" in Library work.
Architecture behavioral of Entity rangesen is up to date.
Compiling vhdl file "C:/Documents and Settings/vial1001/Desktop/New Folder (2)/Copy of s & t-8/project/binary2bcd.vhd" in Library work.
Architecture behavioral of Entity bin2bcd is up to date.
Compiling vhdl file "C:/Documents and Settings/vial1001/Desktop/New Folder (2)/Copy of s & t-8/project/sevensegment.vhd" in Library work.
Architecture behavioral of Entity sevenseg is up to date.
Compiling vhdl file "C:/Documents and Settings/vial1001/Desktop/New Folder (2)/Copy of s & t-8/Rs232 RefProj2/SourceFiles/DataCntrl.vhd" in Library work.
Architecture behavioral of Entity uartl is up to date.
Compiling vhdl file "C:/Documents and Settings/vial1001/Desktop/New Folder (2)/Copy of s & t-8/project/top_module.vhd" in Library work.
Architecture behavioral of Entity top_module is up to date.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <top_module> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <rangesen> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <bin2bcd> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <sevenseg> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <uartl> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <RS232RefComp> in library <work> (architecture <behavioral>).
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <top_module> in library <work> (Architecture <behavioral>).
WARNING:Xst:754 - "C:/Documents and Settings/vial1001/Desktop/New Folder (2)/Copy of s & t-8/project/top_module.vhd" line 162: Unconnected inout port 'tclk' of component 'uartl'.
Entity <top_module> analyzed. Unit <top_module> generated.
Analyzing Entity <rangesen> in library <work> (Architecture <behavioral>).
Entity <rangesen> analyzed. Unit <rangesen> generated.
Analyzing Entity <bin2bcd> in library <work> (Architecture <behavioral>).
Entity <bin2bcd> analyzed. Unit <bin2bcd> generated.
Analyzing Entity <sevenseg> in library <work> (Architecture <behavioral>).
INFO:Xst:1561 - "C:/Documents and Settings/vial1001/Desktop/New Folder (2)/Copy of s & t-8/project/sevensegment.vhd" line 114: Mux is complete : default of case is discarded
WARNING:Xst:819 - "C:/Documents and Settings/vial1001/Desktop/New Folder (2)/Copy of s & t-8/project/sevensegment.vhd" line 107: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<z>
ERROR:Xst:827 - "C:/Documents and Settings/vial1001/Desktop/New Folder (2)/Copy of s & t-8/project/sevensegment.vhd" line 78: Signal z<0> cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.
-->
Total memory usage is 132692 kilobytes
Number of errors : 1 ( 0 filtered)
Number of warnings : 2 ( 0 filtered)
Number of infos : 1 ( 0 filtered)
Process "Synthesis" failed
Thanks in advance
xilinx1001
I am trying to display different sensor readings on 7 segment in a circular sequence
I stored both the sensor readings
But I have problem while displaying the the segemnts.
I saved the sensor readings in two different arrays
Code:
Code:
type dbuff is array (0 to 3) of std_logic_vector(3 downto 0);
signal x:dbuff;
type dbuff1 is array (0 to 3) of std_logic_vector(3 downto 0);
signal y:dbuff1;
type dbuff2 is array (0 to 3) of std_logic_vector(3 downto 0);
signal z:dbuff2;
begin
x(0)<=unit1;
x(1)<=tens1;
x(2)<=hundreds1 ;
x(3) <="0000" ;
y(0)<=unit2;
y(1)<=tens2;
y(2)<=hundreds2 ;
y(3) <="0001" ;
anodes <= r_anodes;
process(segclk,x(0),x(1),x(2),x(3),y(0),y(1),y(2),y(3),z(0),z(1),z(2),z(3))
begin
if rising_edge(segclk) then
z(0)<=x(0);
z(1)<=x(1);
z(2)<=x(2) ;
z(3) <=x(3) ;
else
z(0)<=y(0);
z(1)<=y(1);
z(2)<=y(2) ;
z(3) <=y(3) ;
end if;
end process;Error:
Reading design: top_module.prj
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/Documents and Settings/vial1001/Desktop/New Folder (2)/Copy of s & t-8/Rs232 RefProj2/SourceFiles/RS232RefComp.vhd" in Library work.
Architecture behavioral of Entity rs232refcomp is up to date.
Compiling vhdl file "C:/Documents and Settings/vial1001/Desktop/New Folder (2)/Copy of s & t-8/project/rangesensor.vhd" in Library work.
Architecture behavioral of Entity rangesen is up to date.
Compiling vhdl file "C:/Documents and Settings/vial1001/Desktop/New Folder (2)/Copy of s & t-8/project/binary2bcd.vhd" in Library work.
Architecture behavioral of Entity bin2bcd is up to date.
Compiling vhdl file "C:/Documents and Settings/vial1001/Desktop/New Folder (2)/Copy of s & t-8/project/sevensegment.vhd" in Library work.
Architecture behavioral of Entity sevenseg is up to date.
Compiling vhdl file "C:/Documents and Settings/vial1001/Desktop/New Folder (2)/Copy of s & t-8/Rs232 RefProj2/SourceFiles/DataCntrl.vhd" in Library work.
Architecture behavioral of Entity uartl is up to date.
Compiling vhdl file "C:/Documents and Settings/vial1001/Desktop/New Folder (2)/Copy of s & t-8/project/top_module.vhd" in Library work.
Architecture behavioral of Entity top_module is up to date.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <top_module> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <rangesen> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <bin2bcd> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <sevenseg> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <uartl> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <RS232RefComp> in library <work> (architecture <behavioral>).
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <top_module> in library <work> (Architecture <behavioral>).
WARNING:Xst:754 - "C:/Documents and Settings/vial1001/Desktop/New Folder (2)/Copy of s & t-8/project/top_module.vhd" line 162: Unconnected inout port 'tclk' of component 'uartl'.
Entity <top_module> analyzed. Unit <top_module> generated.
Analyzing Entity <rangesen> in library <work> (Architecture <behavioral>).
Entity <rangesen> analyzed. Unit <rangesen> generated.
Analyzing Entity <bin2bcd> in library <work> (Architecture <behavioral>).
Entity <bin2bcd> analyzed. Unit <bin2bcd> generated.
Analyzing Entity <sevenseg> in library <work> (Architecture <behavioral>).
INFO:Xst:1561 - "C:/Documents and Settings/vial1001/Desktop/New Folder (2)/Copy of s & t-8/project/sevensegment.vhd" line 114: Mux is complete : default of case is discarded
WARNING:Xst:819 - "C:/Documents and Settings/vial1001/Desktop/New Folder (2)/Copy of s & t-8/project/sevensegment.vhd" line 107: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<z>
ERROR:Xst:827 - "C:/Documents and Settings/vial1001/Desktop/New Folder (2)/Copy of s & t-8/project/sevensegment.vhd" line 78: Signal z<0> cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.
-->
Total memory usage is 132692 kilobytes
Number of errors : 1 ( 0 filtered)
Number of warnings : 2 ( 0 filtered)
Number of infos : 1 ( 0 filtered)
Process "Synthesis" failed
Thanks in advance
xilinx1001