schematic .ucf file implementation error

When i floor plan the constraints for CPLD device ,i am getting this error ,can anyone tell me the remedy for this .thanking you






Compiling vhdl file "G:/lokeshwarn/jc2_sch/jc2_top.vhd" in Library work.
Entity <FDC_MXILINX_jc2_top> compiled.
Entity <FDC_MXILINX_jc2_top> (Architecture <BEHAVIORAL>) compiled.
Entity <FJKC_MXILINX_jc2_top> compiled.
Entity <FJKC_MXILINX_jc2_top> (Architecture <BEHAVIORAL>) compiled.
Entity <M2_1_MXILINX_jc2_top> compiled.
Entity <M2_1_MXILINX_jc2_top> (Architecture <BEHAVIORAL>) compiled.
Entity <SR4CLED_MXILINX_jc2_top> compiled.
Entity <SR4CLED_MXILINX_jc2_top> (Architecture <BEHAVIORAL>) compiled.
Entity <jc2_top> compiled.
Entity <jc2_top> (Architecture <BEHAVIORAL>) compiled.
ERROResignEntry - Could not apply constraint: NET left LOC=P1;

ERROResignEntry - Could not apply constraint: NET right LOC=P6;

ERROResignEntry - Could not apply constraint: NET stop LOC=P9;

ERROResignEntry - Could not apply constraint: NET clk LOC=P22;

ERROResignEntry - Could not apply constraint: NET q<0> LOC=P76;

ERROResignEntry - Could not apply constraint: NET q<1> LOC=P77;

ERROResignEntry - Could not apply constraint: NET q<2> LOC=P78;

ERROResignEntry - Could not apply constraint: NET q<3> LOC=P79;

you can't apply your output and input to any port that you want. for example you can apply clock to only
some pins, not to all. probably these errors because of this matter.

ahmad1954 said:

you can't apply your output and input to any port that you want. for example you can apply clock to only
some pins, not to all. probably these errors because of this matter.

Click to expand...

thanks Mr.ahmad ........