schematic problem in formlity

[nawaz.mjcet]

HI all,
while doing formality i'm facing problem in schematics as follows:

there is a flip flop(in schematics) whose inputs and outputs are
AC(asynchronous clear )
SL(synchronous load)
SD(synchronous data)
CLK(clock)
Q(D output)
QN(negation of output )


but the same flip flop in netlist have input and output pins as follows:
D(data)
CLK(clock)
RST(reset)
Q(output)
QN (negation of output)

the SL pin in schematics flop is missing in netlist flop,why is the tools showing a pin in schematics which is not in netlist and for the existing pins also the names are not same....???...please kindly reply....

Thanks in advance,


Regards,
-Nawaz.

 

[tariq786]

when you say netlist, does it mean, synthesized gate level netlist? Can you post the netlist code? When you say schematic, do you mean schematic inside formality? or some other schematic drawing tool?
How do you generate the netlist? Which tool?

Please write a comprehensive reply.

 

[anantha.bhat]

It would have helped if you are referring to RTL to Gate Equivalence checking or Gate to Gate .Indications are it is RTL2Gate. If so, first one could be a generic model of a sequential element derived from interpreting RTL code. Don't look for 1 to 1 correspondence between these pins. Is realized functionality same is all that tool is concerned with.

 

[sam536]

Are you using the .lib or .v files for FV?. Use the .lib and check it and may resolve the issue. It might be linking issues. you may be uising .db files or any other format for netlist in verilog and FV. Use the same for both the versions and check . I mean, what ever u used to write the verilog netlist, use the same lib(either .lib or .v or etc) in formality, this mismtach will go away.

Regards, Sam