Schematic for interwire crstalk&delay measurement![help]

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cadenceUK

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Please suggest me !

The circuit gives attenuated value for same bit patteren and devastating output at opposite bit patteren!
 

Oh! I finally resolved the thing and checked that i was missing the power supply!

Now , I am wondering about the place where i should give the supply?

@ top level
OR
@ inverter level
OR
Both?

Thx in anticipation.
 

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