Schematic and post layout performance difference in 65nm

40nm performance gate delay

Hi,

I am working in 65nm technology and I have a problem with the post layout and schematic performance difference. Take an example of the conventional transmission gate based mux, the post layout simulation has a performance degradation of at least 30% over the schematic simulation. I am wondering if anyone else has the similar situation?

Thanks,

metal width in 65nm

As technology progresses towards 65nm, 45nm technology nodes and beyond, parasitics are playing larger and larger role. 30% discrepancy for 65nm technology does not look unusual. You can expect even a bigger impact of parasitics in 45-40nm technology. What's also interesting, is that different parasitic extraction tools may give you drastically different results...

65nm performance

How about reviewing the layout....????..... More parasitic may lead to performance degradation.....

monte carlo tranny schematic

Need to also consider the greater leakages of the 65nm and beyond technologies. Transmission gates can be particularly sensitive if using min L. You should always simulate best/worst case corners for these technologies (or monte carlo) as a single simulation at nominal temperature will always outperform reality.

45nm 65nm performance

Hi,

First of all thank you for your replies. As timof mentioned, it does seem that 30% is not unusual (especially for complicated logic gates such as XOR).

To Timof:

Can you please elaborate a bit more on how the transmission gate can be particularly sensitive using min L in 65nm technology?

65nm metal width pitch

pichuang said:

To Timof:

Can you please elaborate a bit more on how the transmission gate can be particularly sensitive using min L in 65nm technology?

Click to expand...

Hello -

I am not saying that it is (only) a transmission gate that is sensitive to parasitic. Any MOS transistor with small gate length is sensitive to parasitic R (gate resistance and metal/contact resistances for source/drain) and C (capacitance between poly and contacts, diffusions, and M1).

As an example, I attach a snapshot of one cell from 45nm standard cell library (Nangate in this case) that show the real geometry - you can see that the gate/contacts look like Manhattan buildings, so the parasitic capacitance plays a very significant role. It appears very unlikely the that pattern matching tools (i.e. standard parasitic extraction tools) would be able to calculate accurately capacitances for these 3D structures.

There was a paper at 1995 IEDM (by Intel's Mark Bohr) saying that metal interconnects will become a limiting factor in further VLSI scaling down. It appears that 65nm and 45nm technologies is where/when the real pain from parasitics starts showing up.

Max

performance degradation layout

Timeof is right.... after 90nm ,your interconnect parasitic domintes your device parasitics.....
timeof,can u share that useful paper (intel's) indicated in your previous post ??

deepak.

and gate layout schematic

Interconnect scaling - the real limiter to high performance ULSI

Bohr, M.T.
Portland Technol. Development, Intel Corp., Hillsboro, OR, USA;
This paper appears in: Electron Devices Meeting, 1995., International
Publication Date: 10-13 Dec. 1995
On page(s): 241 - 244

Abstract
Reducing interconnect pitch improves layout density, but degrades interconnect RC delay. Increasing metal aspect ratio (thickness/width) improves RC delay, but maximum benefits are achieved at an aspect ratio of ~2. Adding more interconnect layers improves density and performance, but practical limits are reached in just a few generations. New conductor and dielectric materials and improved circuit design techniques will be needed to meet future ULSI interconnect requirements.

65nm metal capacitance

timof said:

Interconnect scaling - the real limiter to high performance ULSI

Bohr, M.T.
Portland Technol. Development, Intel Corp., Hillsboro, OR, USA;
This paper appears in: Electron Devices Meeting, 1995., International
Publication Date: 10-13 Dec. 1995
On page(s): 241 - 244

Abstract
Reducing interconnect pitch improves layout density, but degrades interconnect RC delay. Increasing metal aspect ratio (thickness/width) improves RC delay, but maximum benefits are achieved at an aspect ratio of ~2. Adding more interconnect layers improves density and performance, but practical limits are reached in just a few generations. New conductor and dielectric materials and improved circuit design techniques will be needed to meet future ULSI interconnect requirements.

Click to expand...

thansk for the detials... I got the papaer.... nice one..
cheers...

impact of post layout parasitics

check your simulation parameter eg when using ELDO as simulation, simulation tunning (smooth, BE...) High standard ... wil give a big shift

g@fsos