[SOLVED] scattering parameters of transistor

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mig-11101

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scattering parameters of a transistor

Could anyone help me on following:

If I have scattering parameters of FET transistor. They are given for some DC point Vds, Id.

From definition, S21 is voltage gain with characteristic load. From that i know, to define voltage gain of transistor, you do need to define supply voltage and decay resistor Rd first. Also output resistance of common-source FET should be dependent on Rd, so it should define matching networks.

How does it comes, that s-params are given just with Vds,Id?

I'd appreciate any help on this, thanks in advance!
 

I think the given scattering parameters of FET transistor are usually measurements. During the measurements, the gate and the drain are loaded by 50 Ohm, which is the port impedance of VNA. And the transistor is biased through biasTee, which is inserted between transistor ports and VNA ports. If the biasTee is ideal, the Rd you meantioned above is infinite. In real case, it's also a enough large value according to the 50 Ohm load. So everything refers to 50 Ohm.
Because the s parameters are different under different bias condition, the s parameter is related to the bias point.
 
Thanks, hxtsz15

If Rd is infinite, how does the power gets from source to the load? Transistor itself is not a power source, its just tunable resistance controlled by Vgs.
**broken link removed**
This is how do i see such circuit for AC..

PS.: that probably is very stupid question, but I just cant get with it..
 
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FET transistor can be considered as a voltage controlled current source.
 
Yep. But how does it explains the question?

Let me try to give an example of what i cant understand -

If I have defined, that S21 is 3.0 magnitude, and I have following circuit
**broken link removed**
Where R1=R2=50[Ohm]

If I have biased my transistor for given S21 on given radio frequency. Then in case of giving 1mV AC on the input, i should get 3mV AC on R2. (Consider it is linear and C1,C2 are short on given frequency)
How does the power gets on R2, if L2 on given frequency acts as open circuit? (Yes, Rd plus reactance is infinite, or very large number, as You told above).
 

mig-11101 said:
Transistor itself is not a power source, its just tunable resistance controlled by Vgs.
Click to expand...
This is your misunderstanding point.
If FET's operation point is in a triode region, drain-source works as variable registor controlled by Vgs, as you think.

If FET's operation point is in an active region (=saturation region), drain-source works as current source controlled by Vgs.

mig-11101 said:
How does the power gets on R2, if L2 on given frequency acts as open circuit?
Click to expand...
Drain of FET acts as current source controled by Vgs.
So the power is surely supplied to R2, even if L2 acts as open circuit.
**broken link removed**)
hxtsz15 said:
FET transistor can be considered as a voltage controlled current source.
Click to expand...
 
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As you say, the S-parameters refers to 50Ohms, but more generally to the reference impedance of the measurement system.
For this, the S-parameters are normalized to the reference impedance when exported and thus they become from the impedance. We talk about "generalized S-parameters".
By this way, you can use it in a circuit simulator and use any load you want, because the S-parameters are normalized.

---------- Post added at 21:47 ---------- Previous post was at 21:43 ----------
Do not forget the transistor effect: it amplifies the signal it receives on its gate. The supply characterized by Vds and Id are just the fuel of the engine !
 
Thanks for answers!

If there is real current source in place of transistor, then everything is clear. But this current source is just equivalent for current change flowing from Vdd, isn't it? So Vdd gives alternating current and constant voltage.. then inductor should block this current changes?
 


Vdd gives the potential of the drain current generation, but the variation of the current is controlled by the gate voltage. This variation of current is blocked by the inductor and flows through the load, which is actually the signal amplified (or generated) from the transistor.
 
So, if I have for example, DC mode Id=10mA and Vds=2V, if I give Vgs such, that it should change Id by +1mA, then I will have Id=11mA, Iload=-1mA and current from the Vdd source stays same DC 10mA? Still, im a bit confused then about voltages - if load is 50 Ohms and -1mA than voltage drop on the load should be -50mV, for AC transistor and load are parallel, means there should be also AC voltage drop on Vds by -50mV? So with given Vds=2V we need to get Vds=1.95, how do we get voltage change, if Vdd is constant on Rd?
 

Your voltage and current calculations are void, because S-parameters are small signal parameters. When describing non-linear devices like transistors, they are valid only for small variations around a specified operation point. Transistor S parameters don't allow conclusions for other than the given operation point.
 
Could you be more precise, please? Places where i meant S parameters, i did meant that there is some given operation point and transistor is working in linear mode..
 

i did meant that there is some given operation point and transistor is working in linear mode..
Click to expand...
Then you don't need to care for Id absolute value, just use AC currents and voltages in calculation.
 
Yep, so my question is - where from appears AC voltage on load resistor and transistor, if AC voltage drop on R3 appears to be 0, Vdd is DC source and the only thing transistor is getting from Vdd is DC Vds?
How does it appears that from DC Vds you can get VdsDC+VdsAC>VdsDC?
 

Under the assumptions you made (L1, L2 act as open circuit, C1 and C2 as short), the circuit in post #5 corresponds to exactly the setup, that's used for S-parameter measurement. So |S21| = 3 results in a voltage gain of 3, assuming only small values of S11. Real impedances of the L and C elements will slightly change the behaviour.

P.S.: S-parameter analysis simply assumes, that the described two-port is able to source AC voltage respectively current. It's treated as a black box, you don't need a think about a supply voltage. In so far all consideration from post #3 are unnecessary.
 
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Thanks for your answer FvM!

Could you please explain, where from does in the circuit in post #5 appears on transistors decay VdsDC+|3xVgs| if there is applied only VdsDC? There should be moments, when Vds is larger then VdsDC, and this means that there should be voltage divider on other resistor of which there is VdsDC-Vds voltage less.. Kirchhoff's voltage law cant be avoided..
 

In my view, you're still confusing large signal with small signal analysis.
You have a bias circuit, that sets an operation point accorfing to your specification. The bias circuit must be suffcient high impedance, the it can be ignored in the AC measurement (strictly spoken it's not so ideal, but it can be eliminated in the impedance analyzer calibration).

Once the bias circuit cares for the operation point, you can apply small AC voltages and make impedance and gain measurements.
 

You are right, but I think it's better replace the 'Rd' by an enough large inductor, then it will be more clear. The inductor blocks the AC component. Indeed, there is a voltage drop between the inductor (Vdd-Vds), however, the ideal inductance is infinite, so the AC current passing through is zero.
 
I think, finally, I have understood how does this works. Made some transient simulations on computer and checked oscillograms at different circuit nodes, also your posts helped!
Thanks for help everyone!
 

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