scan mode input/output delay constrain

I think...DFT Engineer no need to worry about this setup timing for your described specific case...Because this can be check at two levels :
1) We are doing the simulation with timing information...so if any problem occurs..we can know at the simulation with timing.
2) STA engineer need to clear the Timing for Both mode i.e. Test and functional mode..

maulin sheth said:

I think...DFT Engineer no need to worry about this setup timing for your described specific case...Because this can be check at two levels :
1) We are doing the simulation with timing information...so if any problem occurs..we can know at the simulation with timing.
2) STA engineer need to clear the Timing for Both mode i.e. Test and functional mode..

Click to expand...

Your statement #2 is where SID/SOD come into picture right? To clear the timing for test mode, proper SID/SOD need to be set for scan input/output. It goes back to the original question where SID/SOD translation is needed since there is a difference between scan operation and STA process. Maybe I am getting confused abt this. Any comment?

During STA, if timing is not match for SID/SOD....thn STA engineer need to clean the timing also...So they are clearing the timing violation....
Because for testing...the timing closure is also required...

assuming the following waveform @50MHz clock:
Scan input: 0/1 { '0ns' D; }
Scan clock: P { '0ns' D; '5ns' U; '15ns' D; }

What is the SID setting?

SID is not only depends on the Clock but it also depends on the combo logic before the first scan ffs.That's why if you run any simulation with scan patterns, you can see that first three or four cycle are just setup..no transition on those cycles...So to clear STA for first flop. we require some more time.

I guess I am more confused now.

assuming the following waveform @50MHz clock:
Scan input: 0/1 { '0ns' D; }
Scan clock: P { '0ns' D; '5ns' U; '15ns' D; }

AND, assume data delay from scan input pad to first scan FF is 2ns, what will be the SID setting for scan input?

Think that...First clock cycle is just 0..during this..the input is reached up to the input of first scan ff.SO in the second clock cycle, the ffs stored bit is the input which we have given at top level scan input...so the first vector is always blank that called the test setup...

maulin sheth said:

Think that...First clock cycle is just 0..during this..the input is reached up to the input of first scan ff.SO in the second clock cycle, the ffs stored bit is the input which we have given at top level scan input...so the first vector is always blank that called the test setup...

Click to expand...

Are you saying that for N-scan shift, it will take N+1 cycles? So, if I have 4 bits 0101 to shift in, it will be:
Input 0 1 0 1 d
Clock 0 P P P P

The above does not match my understanding though.

Have you any scan patterns? If yes thn just simulate it with the design without timing and with timing..
Thn you can have better understand...

Yes, I deal with scan pattern before, and I am seeing (from vector file, and simulation too) that there is exactly N cycles for N scan cells.
Other ppl deal with STA timing constraint, but this time I need to understand more on how to set proper SID/SOD for scan in/out.

assuming the following waveform @50MHz clock:
Scan input: 0/1 { '0ns' D; }
Scan clock: P { '0ns' D; '5ns' U; '15ns' D; }

AND, assume data delay from scan input pad to first scan FF is 2ns

Per ur experience, what will be the SID setting for scan input?

Why you can not check on the waveform of the simulation that you have done...You can check it from the first cycle..so you can understand how it will work...

I can't understand, if you have simulation waveform thn why you are not able to understand...

ATPG pattern are in the following order:
test_setup -> shift -> capture -> shift -> capture ...

test_setup is for chip level initialization, not for scan shift value stabilization. Furthermore, test_setup is not executed for subsequent shift (which first scan in data does apply)

This thread is about input/output delay constraint setting, however it has been deviated / mis-led.

assuming the following waveform @50MHz clock:
Scan input: 0/1 { '0ns' D; }
Scan clock: P { '0ns' D; '5ns' U; '15ns' D; }
Let internal clock latency to be 1ns

Case #1:
Data delay from scan input pad to first scan FF is 2ns

Total data delay = 2ns
Total clock delay = 5ns (first clock edge) + 1ns = 6ns

Total data delay < total clock delay, setup is met (omit Tsu for simplication)

Case #2:
Data delay from scan input pad to first scan FF is 7ns

Total data delay = 7ns
Total clock delay = 5ns (first clock edge) + 1ns = 6ns

Total data delay > total clock delay, setup is violated (omit Tsu for simplication)

Come back to SID/SOD setup, PT STA process use them in the following way:
SID + data delay < Tper + clock delay

To reflect the actual scenario, SID = Tper - first clock edge = 20 - 5 = 15ns

Revisit case study:
Case #1:
Data delay from scan input pad to first scan FF is 2ns

SID (15ns) + data delay (2ns) < Tper (20ns) + clock delay (1ns), so setup is met

Case #2:
Data delay from scan input pad to first scan FF is 7ns

SID (15ns) + data delay (7ns) > Tper (20ns) + clock delay (1ns), so setup is violated

I believed that should be the right way instead of hoping for test_setup or simulation. However, I do agreed that timing simulation is important to catch setup/hold issue.

I am telling you to hope for simulation because what you have shown in the last thread....that all things you can see in the waveforms.
If you do simulation with timing, thn all the delays like : combo logic delay, pad delay, wire delay.....all are covered..so rather to think this much..you can understand this with the simulation waveform easily....

maulin sheth said:

I am telling you to hope for simulation because what you have shown in the last thread....that all things you can see in the waveforms.
If you do simulation with timing, thn all the delays like : combo logic delay, pad delay, wire delay.....all are covered..so rather to think this much..you can understand this with the simulation waveform easily....

Click to expand...

Back to square one, this thread is about setting the proper SID/SOD, and it can be simplified as
SID = Tperiod - first clock rising edge

maulin sheth said:

SID is not only depends on the Clock but it also depends on the combo logic before the first scan ffs.That's why if you run any simulation with scan patterns, you can see that first three or four cycle are just setup..no transition on those cycles...So to clear STA for first flop. we require some more time.

Click to expand...

maulin sheth said:

Think that...First clock cycle is just 0..during this..the input is reached up to the input of first scan ff.SO in the second clock cycle, the ffs stored bit is the input which we have given at top level scan input...so the first vector is always blank that called the test setup...

Click to expand...

This reply is mis-leading. test_setup has nothing to do with scan input stabilization.