Scan converter look up table issue

Hello I am implementing a code for Scan converter which involves the construction of look up tables.
I am using Altera Quartus II for simulation. I have shown the code below, but I am having problems with the look up table instantiation.
This involves sin LUT - for sin theta operations and cos LUT for cos theta operations. Kindly help.....


library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use IEEE.std_logic_signed.all;

entity ScanCnvtrModule is

port
(
Clk : IN STD_LOGIC; -- clock 50 MHz
rstn : IN STD_LOGIC; -- asynchronous active low reset
Prt : IN STD_LOGIC;
theta : IN STD_LOGIC_VECTOR(11 downto 0);
RngClr : IN STD_LOGIC;
VideoPulse : IN STD_LOGIC;
Zoomfactor : IN STD_LOGIC_VECTOR(9 downto 0);
Video_threshold : IN STD_LOGIC_VECTOR(8 downto 0);
x_origin : IN STD_LOGIC_VECTOR(11 downto 0);
y_origin : IN STD_LOGIC_VECTOR(11 downto 0);
MaxScanCnvtrRngBinCnt : IN STD_LOGIC_VECTOR(15 downto 0);

dpram_wr_addr : OUT STD_LOGIC_VECTOR(13 downto 0);
dpram_data : OUT STD_LOGIC_VECTOR(35 downto 0);
wr_enable : OUT STD_LOGIC
);

end ScanCnvtrModule;

architecture architecture_ScanCnvtrModule of ScanCnvtrModule is

component DPROM1
PORT
(
address_a : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
clock : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
end component;

component DPROM2
PORT
(
address_a : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
clock : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
end component;


signal ScanConverterClkCnt : std_logic_vector(9 downto 0);
signal Zoomfactor_sig : std_logic_vector(9 downto 0);
signal ScanConverterRngBinCnt : std_logic_vector(15 downto 0);
signal RngSintheta : std_logic_vector(28 downto 0);
signal RngCostheta : std_logic_vector(28 downto 0);
signal theta_sig : std_logic_vector(11 downto 0);
signal Cos_theta : std_logic_vector(11 downto 0);
signal Sin_theta : std_logic_vector(11 downto 0);
-- signal Video : std_logic_vector(7 downto 0);
signal Video : std_logic_vector(8 downto 0);
signal x_addr, y_addr : std_logic_vector(11 downto 0);
signal PRT_sig : std_logic;
signal dpram_wr_addr_sig : std_logic_vector(13 downto 0) := (others => '0');


-- Scan Converter States
type STATE_TYPE2 is (IDLE,START,CALCULATE1,CALCULATE2,STORE);
signal STATE_SCANCONVERTER : STATE_TYPE2;


begin



---------------------------------------------------------------------------------------------------------
-- Scan Converter Module
---------------------------------------------------------------------------------------------------------
Zoomfactor_sig <= Zoomfactor;
PRT_sig <= Prt;
wr_enable <= '1';

-- 90 Km = 500 pixels
-- which means 1 pixel = 0.18 Km = 180 mtr

-- 30 mtr = 200 nsec
-- 180 mtr = 1200 nsec
-- Clk used in this module is 100 MHz... which means T(period) = 10 nsec
-- Zoomfactor = (1200 nsec)/(10 nsec) = 120 Cnts



--------------------------------------------------------------------------
ScanConverterModule : process ( Clk )

begin

if ( Clk 'event and Clk = '1') then

if( rstn = '0' ) then
STATE_SCANCONVERTER <= IDLE;
else
case STATE_SCANCONVERTER is
--------------------------------------------------------------------------
when IDLE =>

if( PRT_sig = '1' ) then

ScanConverterClkCnt <= (others => '0');
ScanConverterRngBinCnt <= (others => '0');

STATE_SCANCONVERTER <= CALCULATE1;

end if;
--------------------------------------------------------------------------
when START =>

if( PRT_sig = '1' ) then
ScanConverterClkCnt <= (others => '0');
ScanConverterRngBinCnt <= (others => '0');

elsif( ScanConverterClkCnt = (Zoomfactor - 1) ) then
ScanConverterClkCnt <= (others => '0');
ScanConverterRngBinCnt <= ScanConverterRngBinCnt + 1;

STATE_SCANCONVERTER <= CALCULATE1;
else
ScanConverterClkCnt <= ScanConverterClkCnt + 1;
end if;
--------------------------------------------------------------------------
when CALCULATE1 =>

ScanConverterClkCnt <= ScanConverterClkCnt + 1;

if( ScanConverterClkCnt = 1 ) then
-- X & Y Components Calculation
RngSintheta <= ('0' & ScanConverterRngBinCnt) * Sin_theta;
RngCostheta <= ('0' & ScanConverterRngBinCnt) * Cos_theta;
----------------------------------
if(RngClr = '1') then

if(VideoPulse = '1') then
Video <= (others => '1');
else
--Video <= '1' & x"fe";
Video <= '0' & x"ff";
end if;

-- Video <= '1' & x"ff"; -- <= (others => '1');

STATE_SCANCONVERTER <= CALCULATE2;
else
Video <= (others => '0');
STATE_SCANCONVERTER <= IDLE;
end if;
----------------------------------
end if;
--------------------------------------------------------------------------
when CALCULATE2 =>

ScanConverterClkCnt <= ScanConverterClkCnt + 1;

if( ScanConverterClkCnt = 2 ) then
-- For PPI Scope
x_addr <= x_origin(11 downto 0) + RngSintheta(22 downto 11);
y_addr <= y_origin(11 downto 0) - RngCostheta(22 downto 11);
-- remove 11 bits (in RngSintheta and RngCostheta...)accounted by multiplying 2^11 = 2048 to avoid fractions...
STATE_SCANCONVERTER <= STORE;
end if;
--------------------------------------------------------------------------
when STORE =>

ScanConverterClkCnt <= ScanConverterClkCnt + 1;

-- Write the Scan Converter, Sampled Value into DPRAM
if( ScanConverterRngBinCnt < MaxScanCnvtrRngBinCnt ) then
-- MaximumScanConverterRngBinCnt is line length (or Beam length) in terms of pixels
-- if( x_addr < H_PIXELS and y_addr < V_LINES ) then -- Should be within resolution
dpram_data <= '0' & y_addr(10 downto 0) & '0' & x_addr(10 downto 0) & "000" & Video;
-- Video starts from bit no. 0 and ends at bit no. 8... and bit no. 9, 10 , 11 are dummy
-- Video intensity is of 9 bits (in range)
-- X address starts from bit no. 12 and ends at bit no. 22... and bit no. 23 is dummy
-- Y address starts from bit no. 24 and ends at bit no. 34... and bit no. 35 is dummy
dpram_wr_addr_sig <= dpram_wr_addr_sig + 1;
-- end if;
STATE_SCANCONVERTER <= START;
else
STATE_SCANCONVERTER <= IDLE;
end if;
--------------------------------------------------------------------------
when others =>
STATE_SCANCONVERTER <= IDLE;
end case;

end if;
end if;
end process;

-- Bit no. (30 downto 20) represents Y addresss
-- Bit no. (18 downto 8) represents X addresss
-- Bit no. (7 downto 0) represents Video
-- Bit no. 19 and 31 represents dummy

dpram_wr_addr <= dpram_wr_addr_sig;

Sin_LUT : DPROM1
PORT MAP
(
address_a => theta,
address_b => (others => '0'),
clock => Clk,
q_a => Sin_theta,
q_b => open
);


Cos_LUT : DPROM2
PORT MAP
(
address_a => theta,
address_b => (others => '0'),
clock => Clk,
q_a => Cos_theta,
q_b => open
);


end architecture_ScanCnvtrModule;

You should post code with syntax or code tags

You should create a ROM megafunction and use a mif file with your sine and cosine data.

See this for mif file format: http://quartushelp.altera.com/9.1/mergedProjects/reference/glossary/def_mif.htm

e.g.


Regards

nice and easy way, would be to create function that returns rom values and initiate constant rom register through that function in vdhl code