Scan Chain Reordering

[shahal]

Here is a DFT question:

How would you reorder a scan chain so that there is no Hold violations?

 

[cheelgo]

Here is a DFT question:

How would you reorder a scan chain so that there is no Hold violations?

let me put like this,
most interest would like to get STA check
then do timing ECO.
in general, we don't do reorder after synthesis.

 

[kbulusu]

your question is too open and general. Most tools for example blast fusion automatically re-orders the scan chain and one of the primary objectives to minimize the wirelength of the scan chains. If you do have hold violations, you can always restrict the tool from re-ordering certain scan segments with in the scan chains or some tools have the capability to specify the order of the flops in the scan chain. Read your tool documentation.

 

[shahal]

Let me rephrase... There is supposedly a way where you can re order a scan chain and not have to worry about any hold violations.. I am trying to figure out the concept behind it.. There is a snug paper on it, unfortunatly I do not have access to solvenet any more.

Added after 13 minutes:

in general, we don't do reorder after synthesis.

I think this depends on the tool right? It depends on where you are doing your synthesis, you definatly have to do some sort of scan chan re ordering if you have congestion.. and that is after Synthesis in your physical layout environment.

 

[kbulusu]

In Most cases, yes, there will be a way to instruct the tool to re-order scan chain in such a way as to have min or no gold violations. There is no thumb rule for this, it depends on the design and DFT methodology and flow used. yes, one of the reasons why scan reordering is done to reduce the wirelength of the scan chain sothat it will not create any congestion.

Let me rephrase... There is supposedly a way where you can re order a scan chain and not have to worry about any hold violations.. I am trying to figure out the concept behind it.. There is a snug paper on it, unfortunatly I do not have access to solvenet any more.

Added after 13 minutes:

in general, we don't do reorder after synthesis.

I think this depends on the tool right? It depends on where you are doing your synthesis, you definatly have to do some sort of scan chan re ordering if you have congestion.. and that is after Synthesis in your physical layout environment.

 

[dr_dft]

Theoretically speaking, you can figure out the clock insertion delays to every flip-flop, sort the clock insertion delays from the longest to the shortest, and reordered the scan chains accordingly. This will guarantee that there is no hold time violations, assuming that the hold time requirement on the SI input of your flip-flops is 0ns or less.
Practically, this is not the best way, since it will still lead to long clock routes.
The best thing to do is to look at the clock trees, and do a bottom up approach by stitching all flip-flops from the same clock branch first. The theory is that FFs in the same branch must be physically close to each other, and have minimum skew, meeting both scan reordering criteria.

 

[cheelgo]

Theoretically speaking, you can figure out the clock insertion delays to every flip-flop, sort the clock insertion delays from the longest to the shortest, and reordered the scan chains accordingly. This will guarantee that there is no hold time violations, assuming that the hold time requirement on the SI input of your flip-flops is 0ns or less.
Practically, this is not the best way, since it will still lead to long clock routes.
The best thing to do is to look at the clock trees, and do a bottom up approach by stitching all flip-flops from the same clock branch first. The theory is that FFs in the same branch must be physically close to each other, and have minimum skew, meeting both scan reordering criteria.

hi dr_dft, this is divid and conquer strategy widely used. also sometime introduce more than one (e.g. two/three scan clock) to ease timing issue for scan shift and capture.
many thanks,
cheelgo

 

[dr_dft]

Also, Cheelgo, since you are from IBM, you should know that the only way to guarantee no scan hold time violations is to use LSSD