scan chain reordering

[cooldude040]

scan chain verilog

SCAn chain reordering............... what is meant by this...and on what basis the physical design engineer has to reorder this and wt is this purpose??

 

[shavakmm]

based on timing and congestion the tool optimally places standard cells. While doing so, if scan chains are detached, it can break the chain ordering (which is done by a scan insertion tool like DFT compiler from Synopsys) and can reorder to optimize it.... it maintains the no. of flops in a chain

 

[dft_guy]

hold issues with scan chain reordering

That's right - during placement, the optimization may make the the scan chain difficult to route due to congestion, so the tool will re-order the chain to reduce the amount of metal it takes to get from one flop to the other. This sometimes exacerbates hold time problems in the chain, so buffers may have to be inserted into the scan path. It may not be able to maintain the scan chain length exactly - and it cannot swap cell from different clock domains.

This is usually no problem to the ATPG - you just read the new netlist, and re-generate patterns.

John
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[csmode]

scan chains reordering file

typically how many FF consider while inserting scan chans.in 65nm

 

[dft_guy]

typically how many FF consider while inserting scan chans.in 65nm

Is there a question there? Please clarify...

John

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[rajesh9999]

"typically how many FF consider while inserting scan chans.in 65nm"

Scan chain length (if thats waht you mean) is dictated by Tester memory constraints and not technology node. Several thousands but I do not know the ballpark number.

 

[sekapr]

reorder the scan cells to minimise timing

 

[mujju433]

Why do we convert DEF file to verilog ??
The answer is if at all we are not able to control the ongestion then we will give our netlist back to DFT encineer so tht he can modify the scan chains again
But why to convert from DEF to verilog we can directly give the netlist which we import am i right??

 

[samirkag]

Scan chains are long shift registers for atpg purposes. Since these chains are stitched pre-layout, these need not be layout friendly. Without re-ordering of chains, scan chains contribute to a long total wirelength. From a routability perspective it is important to reduce total wirelength. This reduces (limited) metal demand and acts to reduce congestion. (Refer Sarrafzadeh, Wong et al). Stray chains (unordered) may require repeaters and an increase in utilization. Although timing issues may not be expected since the chains are merely shift paths running at low atpg shift frequency, this might be an issue if chain quality is too poor.

Buzz if you need more information.

SCAn chain reordering............... what is meant by this...and on what basis the physical design engineer has to reorder this and wt is this purpose??

 

[dft_guy]

Why do we convert DEF file to verilog ??
The answer is if at all we are not able to control the ongestion then we will give our netlist back to DFT encineer so tht he can modify the scan chains again
But why to convert from DEF to verilog we can directly give the netlist which we import am i right??

The DEF file, also known as Scan DEF, is just a definition of the scan chains, and is output by the synthesis tool. Some place and rout tools read this, and use it instead of extracting the scan chains from the Verilog netlist to re-stitch the scan chain after placement. Then after placement and routing, A new verilog netlist is generated which is used for ATPG. So, DEF is not converted to verilog, as you say.

This is exactly the kind of discussion we have at DFT Forum every day. So if you don't get the answer here, check it out!

John
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