Scan chain insertion using Tessent

[ML Tester]

I have synthesized a sequential design using freepdk45 library. I have converted this cell library to the atpg library using Tessent libcomp. But this generated an ATPG library that has no scan cell equivalent for any cell. My aim is to insert scan chain. I am getting the below error while running set_system_mode analysis command in Tessent
Warning: Model 'DFFSR' has no muxscan scan equivalent and is treated as nonscan model
Warning: Scan chains may not be inserted due to memory elements without scan equivalent library models.

How to define scan equivalents in the ATPG library, is there a utility to perform this task? Please help me with this.
Any help is highly appreciated. Hope to hear soon.

Thanks and regards,
Testing enthusiast

 

[ML Tester]

Hi all,
I have solved the above problem by writing the scan cell definition by hand following the instructions in the Tessent cell library manual. But I am still not able to get the scan inserted netlist. The logfile consisting of the commands and their outputs is mentioned below:
command: set_context dft -no_rtl -design_id gate
// command: read_cell_library libcomp.atpglib
// Reading DFT Library file libcomp.atpglib
// Finished reading file libcomp.atpglib
// command: array set params $tessent_user_arg
// command: read_verilog ../itc99/${params(ckt)}_netlist_nan.v
// command: #analyze_control_signals > ../itc99/reports/ctrl.rpt
// command: set_current_design ${params(ckt)}
// command: # dft
// command: set_design_level chip
// command: set_scan_signals -tclk test_clk
// Warning: Pin 'test_clk' does not exist and will be created when inserting test logic
// command: # add_dft_signals shift_capture_clock -source_nodes test_clk
// command: check_design_rules
// Warning: Rule FN1 violation occurs 1 times
// Warning: Rule FN4 violation occurs 5 times
// Flattening process completed, cell instances=47, gates=101, PIs=4, POs=2, CPU time=0.00 sec.
// ---------------------------------------------------------------------------
// Begin circuit learning analyses.
// --------------------------------
// Learning completed, CPU time=0.00 sec.
// command: set_context dft -scan
// command: add_clocks 0 clock reset
// command: set_system_mode analysis
// ---------------------------------------------------------------------------
// Begin scan chain identification process, memory elements = 5,
// sequential library cells = 5.
// ---------------------------------------------------------------------------
// ---------------------------------------------------------------------------
// Begin scannability rules checking for 5 sequential library cells.
// ---------------------------------------------------------------------------
// 5 sequential library cells identified as scannable.
// ---------------------------------------------------------------------------
// Begin scan clock rules checking.
// ---------------------------------------------------------------------------
// 2 scan clock/set/reset lines have been identified.
// All scan clocks successfully passed off-state check.
// 5 sequential cells passed clock stability checking.
// ---------------------------------------------------------------------------
// Begin shift register identification for 5 sequential library cells.
// ---------------------------------------------------------------------------
// No shift registers identified.
// Number of targeted sequential library cells = 5
// command: insert_test_logic
// Warning: No test logic was inserted.
// Warning: Flattened model deleted.

Please help me with this.
Thanks and regards,
ML Tester