SCAN CHAIN for 3 clock.

[VitalyM4]

stuck-at chain test

Hi all!

I have design which has 3 different clocks. I want 3 scan-chain - 1 per clock domain, so I need to mux clocks.

How to instruct DFT to create 3 scan-chain? I should create 3 test protocols and which clock I should describe there, test clock or clock needed for normal operation?

I have not connected null ports in RTL- SCAN_IN_CLK, SCAN_IN_EXTCLK, SCAN_IN_DCLK as test inputs.
SCAN_EN_CLK, SCAN_EN_EXTCLK, SCAN_EN_DCLK as test enable.
SCAN_OUT_CLK, SCAN_OUT_EXTCLK, SCAN_OUT_DCLK as test outputs.

Can I somehow use them for connecting scan-chains?

Best regards.

 

[carv_13]

scan clock

I think you can use the following commands

add scan pins chain1 scan_input1_pin scan_output1_pin -clock pin_name1
add scan pins chain2 scan_input2_pin scan_output2_pin -clock pin_name2
add scan pins chain3 scan_input3_pin scan_output3_pin -clock pin_name3

You can use

insert test logic number option to specify the exact number of scan chains that you want which in this case would be 3.

All these are applicable if you are using dftadvisor. But other tools also would probably have similar commands.

Hopefully this helps.

-Aravind

Added after 2 minutes:

Also I think DFTAdvisor by default assigns different scan chains for different clock domains. So it might actually assign 3 scan chains without you having to specify that number of scan chains. But its always better to specify if you are particular about the number of scan chains.

 

[vlsi_eda_guy]

existing_dft spec

For DFT Compiler you dont need to do anything the tool will do it by itself.

You define the three clocks , by default the number of chains is equal to the number of clock domains. One thing to note is that if you have both posedge and negedge flops on one clock then it becomes to clock domains for DFTC.

To guide the tool to use the specific scan port use the command

set_scan_path ch1 -view spec -scan-data_in <> -scan_data_out <>
set_scan_path ch2 -view spec -scan-data_in <> -scan_data_out <>
set_scan_path ch3 -view spec -scan-data_in <> -scan_data_out <>

 

[shiv_emf]

dft internal pin flow

I have one doubt . Though u have three clock domain u can go for single scan chain .... wht is wrong with single chain?

u have one scan clock rite?

 

[VitalyM4]

scan chain clock domain

I have one doubt . Though u have three clock domain u can go for single scan chain .... wht is wrong with single chain?

u have one scan clock rite?

If it is possible with 1 scan-chan it is good, but how does it impact on ATPG coverage?
Another one small question. SCAN_EN_* signals forms inside SPI/U_test_controller
why command

set_dft_signal -view existing_dft -type ScanEnable -port SPI/U_test_controller/SCAN_EN_SCLK

doesn't accepted?

All my resets form inside one internal module U_reset_form. Should I include them when I create test_protocol?

 

[vlsi_eda_guy]

single scan chain

I have one doubt . Though u have three clock domain u can go for single scan chain .... wht is wrong with single chain?

u have one scan clock rite?

If it is possible with 1 scan-chan it is good, but how does it impact on ATPG coverage?
Another one small question. SCAN_EN_* signals forms inside SPI/U_test_controller
why command

set_dft_signal -view existing_dft -type ScanEnable -port SPI/U_test_controller/SCAN_EN_SCLK

doesn't accepted?

All my resets form inside one internal module U_reset_form. Should I include them when I create test_protocol?

First on single chain: You can have a single chain it will not effect your test coverage the effect will be the tester time. Single chain means more cycles needed for loading and unloading the scan chains. The major time during testing is for load and unload of the chains , if we have multiple short chains then the tester time is reduced. And actually this is the crux of the scan compression techniques.

Now coming to single test clock, it is good if you are doing static testing that is stuck-at testing. If you plan to do the at-speed test then single test clock is a big problem and can lead to pattern inflation.


Further on the command, since you have used the -port it is expecting a top level port of the core/chip depending on what level you are doing the ATPG. If you really want to use the internal pin with out a port then you can enable the internal pin flow of DFT Compiler and then run the same with -hookup_pin and no port .

-vlsi_eda_guy