Scaling intermediate results in HDL DSP Hardware

Hey all,

I'm implementing a recursive DSP algorithm in HDL and having trouble understanding where I must scale my results to avoid over/underflow, and what impact this has on my final result.

This is the data flow for the algorithm I'm implementing (for those of you who are familar with this, it is the recursive part of Goertzel's algorithm)



The input x is unsigned & 12 bits, and I would like to constrain the output y also to 12 bits. A is a constant multiplier (constants are hard coded) which from derivation has a value between ± 2.

Now, if the value of y is 12 bits, this means that the output from the multiplier A would be 13 bits, and negating part should also provide a 13th bit so it can represent a unsigned 12 bit number, in 2's complement 13 bit format.

Then this is added to the next input which could result in the value of y growing until it overflows. How should I constrain/scale this, and is there a formal method which I can calculate the required width of my data paths...

any ideas, references or literature on this topic?