My Digital data range is 14 bit ( 0000 H to 3FFF H). but my DAC resolution is 12 bit. so I need to change the scale to 12 bit. In order to change the scale, what could the best suitable method. Will it be suitable to divide the 14 bit data with 4 to scale down to 12 bit? or any other suitable method can be used in FPGA?
My DAC is DAC2932. which is 12 bit parallel interface. so in parallel DAC , there is no requirement for scaling. I just need to ignore the 2 LSB, Is it like this?
Here the values:
The (average) offset the truncation causes compared to the rounding method is -0.5 LSB
12 bit means 4096 steps full scale, thus one LSB is 0.025% FS ...
--> and 0.5LSB means 0.0125% FS. If we take 1mA as FS, then the error is 0.125uA or 125nA
The DAC datasheet says
the DAC has an Offset error of ±0.001% FS. This is incredibly good. Thus when the DAC output is close to zero the truncation error (of 125nA) dominates.
The gain error is given with +/-0.5% FS typically. Now if we compare gain error with truncation offset error we can say that at 1/40 or 2.5% of output (or higher) the gain error dominates.