adix
Junior Member level 2
Dear all,
I have a problem with the postlayout parasitic extraction in calibre. My design kit recognizes only scaled sizes of transistors, that is, if a 0.5um width transistor is needed I have to put 0.5 instead of 0.5u. The design kit model is scaled by 10^-6. My problem is now with the parasitic extraction: all transistors extracted have not scaled sizes so I cannot use them since spectre shows that the transistor size is below the minimum design rule. The only way to deal with it was to change the transistor sizes of post sim one by one. This would be very long procedure with my large schematic. Is there a smarter way to automaticaly scale all sizes of postsim extraction?
Thanks in advance for the answer!!
I have a problem with the postlayout parasitic extraction in calibre. My design kit recognizes only scaled sizes of transistors, that is, if a 0.5um width transistor is needed I have to put 0.5 instead of 0.5u. The design kit model is scaled by 10^-6. My problem is now with the parasitic extraction: all transistors extracted have not scaled sizes so I cannot use them since spectre shows that the transistor size is below the minimum design rule. The only way to deal with it was to change the transistor sizes of post sim one by one. This would be very long procedure with my large schematic. Is there a smarter way to automaticaly scale all sizes of postsim extraction?
Thanks in advance for the answer!!