SC_TSMC180 library problem

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mehran1367

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hi all,
can we limit design compiler not to use some cells .fore example I want to have an and cell ,a nor cell instead of an AOI cell.is it possible ?(I use SC_TSMC180 library)

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tanx
 

set_dont_use or something like that is a sdc command to indicate which std cell you don't want the synthesizer to used.
 

rca is right, you can go through all your AOI cells in the library and set_dont_use them.

Take into account that excluding such elementary cell from your library may cause very not-optimized design in some cases.
 

Hello everybody
As a matter of fact, I'm new to cadence virtuoso and usually use gpdk180 library to simulate schematics in cadence using ADE (analog design environment). But when I was looking around in my Linux machine, I found a folder named SC_TSMC180 beside my gpdk180 folder and wondered what it is for :!:
I did some googling, but didn't find anything useful about it
Could you explain a little about its usage, and how its related to cadence virtuoso
I would appreciate any documentation or tutorial
Thanks in advance
 

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