Save 2Mbyte sample per second

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Hello
i received 2Mega byte data from my wireless per second and i want to transfer them to my PIC32MX360F512L to check their party bit.but as you know this micro has little Ram and can't received 2Mega byte per second and process on them and finally transfer them to computer.i think to use a memory within micro and my wireless board. but i don't know what ic should i choose and what is the best way to solve my problem.

any help appreciated
 

If the data comes in bursts, you could use a fifo. How big are the bursts? what's the AVERAGE data rate? Unless your AVERAGE data rate is something the PIC can handle, you're going to have problems. Are there cost constraints? How do you intend to transfer the data to a computer? An FPGA or CPLD might be able to solve this problem.
 

Hello barry
Thanks for your response.
It is my university project that works on wireless communication.each sample have 8bit and we have 2Mega byte data per second.can read/write from fifo memory simultaneously with a litte time to read and write on them?

i connect my board to PC via usb protocol.(dspic usb)
 

Please Help me
 

barry said:
How big are the bursts? what's the AVERAGE data rate? Unless your AVERAGE data rate is something the PIC can handle, you're going to have problems.
Click to expand...


Answering those might be a good start to get help.

Case in point, if you get continuous 2 MByte/s and the PIC alone cannot handle that, then you have to think of something. If it is NOT continuous, but burst, see previous questions by barry.
 
Hello mrflibble
my data are burst and maybe be continues in some minutes (transfer a file via wireless communication). could you tell me how adsl modem or digital wireless works with many bites per second?
i want do something same as wireless modem.
 

I have a cunning plan! How about buying a ready to integrate wireless module of your chosen wireless standard, that accepts RX/TX from your PIC. That way you only have to implement an UART, and all the heavy wireless lifting is taken care off.
 

Thanks mrflibble but i design the wirless digital communication i need to know how can received data from receiver circuit and check the check sum of them.
 

If you're just checking parity, do you need to retain all received bytes?

Regarding your DSL question, DSL routers have (reasonably) high performance (higher than your
PIC anyway) processors, and sufficient ROM/RAM to run an OS like Linux. You can't do the equivalent of what
a DSL router does with a PIC with 32K RAM.
So, you'll need to re-think your strategy.
 
baby_1 said:
Thanks mrflibble but i design the wirless digital communication ... i need to know how can received data from receiver circuit and check the check sum of them.
Click to expand...


That seems a curious combination, but okay.
 

Thanks sky_123
as you know if i want to use another memory to store data such as DSL router what can i do?
my output of wireless circuit if 8bit data and we have 2Mega byte per second.
 

Basically the things that were suggested in the first response, i.e. offboard FIFO or RAM. You later stated the transfer could be several minutes but you
didn't specify if you need to retain the data for any purpose. If you did, then to store 2MBps*180sec is 360Mbytes of data.
That is too large for a FIFO ic, but some form of RAM could be used. A DSL router however would not store 360Mbytes of data, it would route the data.

If you want to do what a DSL router does, then you need a faster processor, and just sufficient memory to buffer, route and schedule the packets, not memory
to store the entire 360Mbyte file. DSL routers are calculating a checksum for packets that does not require buffering of the entire file.
 
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hello
as you see the internal circuit of a DSL router they use ARM processor such as A-cortex with high frequency about (200Mhz). how they can received each packet with high speed and process on them while they are receiving?(for example in wireless modems that they speed are about 10Mbit/s or 100Mbit/s)? they processor aren't very fast as FPGA or .... but they received data and check sum each packets?

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hello
as you see the internal circuit of a DSL router they use ARM processor such as A-cortex with high frequency about (200Mhz). how they can received each packet with high speed and process on them while they are receiving?(for example in wireless modems that they speed are about 10Mbit/s or 100Mbit/s)? they processor aren't very fast as FPGA or .... but they received data and check sum each packets?
 

Yes, 200MHz processor can be sufficient. For example, see **broken link removed**.
8Mbit/sec for example is just 1MByte per sec. Also bear in mind that hardware acceleration can be used to perform checksums, etc..
 

options:

1) SoC: arm core with dedicated hardware for ethernet + checksumming
2) external checksum offloading to ethernet chipset
3) checksum in software, since 100 Mbit/s isn't all THAT much.

Just for the fun of it you can take a look at some linux kernel networking code for the checksum.
 

It´s long time since I didnt use PICs. However I implemented a simple RS232 serial transmission between a 16F628A and another board to be controlled by ASCII characters. The only thing I want to add is that I got a lot of helpful information from both the application notes in the microchip website and the microchip forum. I would suggest you to ask the same question in the microchip forum, there are specialized and experienced people that may give you a solution to your problem.

--E
 

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