[SOLVED] SATA controller program execution

[mrflibble]

To prevent any surprised you should first do a Clean project in ISE, and then do that Regenerate all cores again.

And the only error I see is that your shift key is broken. ;-) The "errors" in your screenshot are all warnings, not errors. While it is certainly advisable to read them and know what they are warning you about, quite often they are not a problem. But again, do read them and try to understand what they are about. Because only that way can you make a reasoned decision to ignore the warning, or to do something about it.

And when I say "prevent any surprises", I really mean "reduce the amount of surprises". Clean project still leaves some files strewn around, but it is a lot better than not doing so before a regenerate all cores.

 

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I actually download the project and opened it. The project has 6 errors and all of them are the cores having multiple instances being compiled...namely the filename.v and the filename_synth.v version of the files being used for both simulation and for synthesis.

That is definitely a problem and I have no clue how to fix something like that. Vivado has different directories for sim/syn files and separates them in their own hierarchy in the Hierarchy pane.

FYI, I've never run a simulation through the ISE GUI, so I've never included simulation files in my ISE projects. I've always used ISIM separately from the command line or Modelsim from a command line script.

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To prevent any surprised you should first do a Clean project in ISE, and then do that Regenerate all cores again.

BTW mrflibble, I did a clean project when I discovered the errors and it doesn't help.... I think the cores need to be removed then added again.

 

[mrflibble]

BTW mrflibble, I did a clean project when I discovered the errors and it doesn't help.... I think the cores need to be removed then added again.

Well, there goes that plan. Remove + re-add is a good idea. Or rather, remove cores, clean project, restart ISE, add cores.

Okay, now I am curious as to how it is failing. *download project*

 

[mrflibble]

I just ran the clean + regenerate core circus on ISE 14.7. And get the same type of errors, 6 in total. It is almost as if someone did the following:

- add core (.xco file) to project
- generate core
- copy generated design file to other location
- add those files to project

Because what's up with the "message_fifo" files being in the project root as well as in the "ipcore_dir" directory?

What I would do is make note of all the .xco files that are in use. Copy those to a safe location. Remove all cores from project. Remove all files that look like remnants from those cores. Add those .xco files again. Generate all cores. Run synth again.

I am not going to do that, because it's way too much busy work. But I suspect that's what is needed to clean up the mess. I could very well be wrong, but please tell me the reason why there are message_fifo files both in the project root and the same stuff again in the ipcore_dir. That really does look like someone way just copying + adding to project and then hoping for the best.

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Out of curiosity did the above for 1 .xco, and that didn't help. Same error count. Weird.

 

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write down the core settings (save the xco's) delete the entire ipcoredir and start over with Add New Source->core generator....?

Maybe there's something in the ipcoredir that got moved around by the OP and it's corrupting the distinction between the synthesis and simulation files?

Note: I'm just taking stabs in the dark on this.

 

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The problem is a problem with the 9.2 version of the fifo generator core. If the fifos are upgraded to the latest 9.3 version they are correctly compiled. There is something that is causing both the *.v and the *_synth.v files to be pulled into xst synthesis. Removing the .xco files and adding in the .ngc file allows the build to complete, but will likely break simulations. Even though using ISE 14.7 and the latest version of the FIFO generator core works, you still have to make sure you run synthesis once without the fifo core, it won't synthesize, as that fixes something to do with upgrading the 9.2 version to the 9.3 version, that doesn't seem to fix anything until you remove the core and run synthesis without the core, then add the 9.3 version core back into the design.

So upgrade to ISE 14.7 and the v9.3 fifo generator or use the v9.2 .ngc files with 14.6

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Just had an idea you might be able to add the *.v files but specify they are only to be used for simulation. That's the first option in the dialog box that opens up. I'm not going to try it as I've already closed and deleted the project.

 

[Sunayana Chakradhar]

okay is there any other open source ip cores available which i can use for my virtex 5 or 6 sata device and host implementation?

 

[mrflibble]

Tsk. Giving up because of a minor core related issue? This is something that can be fixed, max estimated time to flush into this is 2 days. Probably a lot less. All the free resources are bound to have some issues. In fact, they will all have something when it comes to core version mismatches. You could always try to use the exact same ISE version as the original project used, and learn from that. Do you know what version ISE was used, before you started to play with it?

 

[Sunayana Chakradhar]

I have actually tried all alternatives available. Even if i delete and recreate the cores, it doesn't seem to work. However I shall try once more to delete the ipcore directory that comes with this program and recreate it. The program was probably created with ISE 12 version. I have ISE 14.6

 

[mrflibble]

It was probably created with ISE 14.2, as determined during my cornflakes because I was curious.

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And the original for V6 from which it was derived, no idea what version ISE that was.

 

[Sunayana Chakradhar]

is it possible that i just create a new project. while using the source codes from univ of massachusettes.I will add my own ip cores and other files. Please instruct me on how to do this?

 

[mrflibble]

Sounds like a decent plan to try. Especially since you mention your target is virtex-6 .. oh wait, wrong university. See, I should not assume things. Reread that page you linked to again. Then you see the other uni being mentioned, and the original design on opencores that is for v6. As for instructions, I am of the school of thought that you first try it yourself several times, fail a few times, try again and only after that you ask. ;-)

 

[mrflibble]

Well, I got it to work. Bitfile and all. But the design as distributed in that .zip doesn't work right out of the box. And after getting it to work I took a look at the webpage again, and nope, the required steps to get it to work are not described there.

Amusing detail is that the design as is doesn't even fit the target board. But if you take sata_core as the top level then you find that this does fit. Then of course the constraints in the ucf are wrong, but that's not a big deal since you can fix the signal names. Or do what I did (being lazy and all that), keep the sata_test wrapper. That way you can keep the same signal names in the ucf. And then just remove the ICON + ILA from that top level. They look like they were plonked in as an afterthought anyways.

Anyways, this was a nice example on how not to distribute work. And a fun exercise of the troubleshooting skills.

In closing, if virtex-6 is your intended target, I would use the original design from opencores.

From that webpage you linked to:
This design is based on a SATA core created at the University of North Carolina at Charlotte for Virtex-6 devices, created by Ron Sass, Ashwin Mendon, and Bin Huang. That design is available here. Some new features have been added in this version, including a replay buffer to improve reliability and new debugging modules.

https://opencores.org/project,sata_controller_core

That's the potentially less fscked up version for V6.

PS: Oh yeah, I used ISE 14.2 since that is what the project in the .zip used. Reduces the amount of surprises.

 

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I have actually tried all alternatives available. Even if i delete and recreate the cores, it doesn't seem to work. However I shall try once more to delete the ipcore directory that comes with this program and recreate it. The program was probably created with ISE 12 version. I have ISE 14.6

is it possible that i just create a new project. while using the source codes from univ of massachusettes.I will add my own ip cores and other files. Please instruct me on how to do this?

As to instructions on how to do "this", read Xilinx's documentation. I'm certainly not going to "read it to you".

Did you follow my instructions or even read my post? The problem is specifically with the 9.2 core. If I didn't run a synthesis with the FIFO cores removed from the project, it would continue to attempt the compilation of both the synthesis and the simulation version of the FIFO generator core. If I ran synthesis with the FIFO cores removed and added the 9.3 core to the project the synthesis would work. If I removed the 9.2 .xco file and added instead the .ngc file for the 9.2 core the synthesis would also work. I suggested trying to add the 9.2 core simulation file for each core back into the project with the settings set to simulation only. But I don't think you tried any of what I suggested, which would FIX your problem.

Why do I even bother trying to help

It was probably created with ISE 14.2, as determined during my cornflakes because I was curious.
And the original for V6 from which it was derived, no idea what version ISE that was.

Sounds like a decent plan to try. Especially since you mention your target is virtex-6 .. oh wait, wrong university. See, I should not assume things. Reread that page you linked to again. Then you see the other uni being mentioned, and the original design on opencores that is for v6. As for instructions, I am of the school of thought that you first try it yourself several times, fail a few times, try again and only after that you ask. ;-)

This is ridiculous if the design was originally a V6 and was back ported to a V4, but they want to port it from a V4 to a V6!?...I think a career in pointy hair management is more appropriate.

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Well, I got it to work. Bitfile and all. But the design as distributed in that .zip doesn't work right out of the box. And after getting it to work I took a look at the webpage again, and nope, the required steps to get it to work are not described there.

Amusing detail is that the design as is doesn't even fit the target board. But if you take sata_core as the top level then you find that this does fit. Then of course the constraints in the ucf are wrong, but that's not a big deal since you can fix the signal names. Or do what I did (being lazy and all that), keep the sata_test wrapper. That way you can keep the same signal names in the ucf. And then just remove the ICON + ILA from that top level. They look like they were plonked in as an afterthought anyways.

Anyways, this was a nice example on how not to distribute work. And a fun exercise of the troubleshooting skills.

In closing, if virtex-6 is your intended target, I would use the original design from opencores.

From that webpage you linked to:
This design is based on a SATA core created at the University of North Carolina at Charlotte for Virtex-6 devices, created by Ron Sass, Ashwin Mendon, and Bin Huang. That design is available here. Some new features have been added in this version, including a replay buffer to improve reliability and new debugging modules.

https://opencores.org/project,sata_controller_core

That's the potentially less fscked up version for V6.

PS: Oh yeah, I used ISE 14.2 since that is what the project in the .zip used. Reduces the amount of surprises.

Wow, you went to an awful lot of trouble...

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I noticed that this student project version isn't the only SATA core on opencores. Another V6 version, which looks to be a project by either a working engineer/consultant or a knowledgeable hobbyist with a lot of experience. Plus I like the fact they have an AXI version available.

 

[mrflibble]

This is ridiculous if the design was originally a V6 and was back ported to a V4, but they want to port it from a V4 to a V6!?...

I agree that porting the backport to the original platform is a tad silly. :grin: The only reason I'd usually consider something like that is if the backport really is more like a fork, and the fork had useful additions, bug fixes, etc. But hey, you can always hope to learn something from said backport, and then carry that over to the original. In this case the backport had a few counter-examples on distribution. This one looks like zip it, ship it, and definitely do NOT test it.

Wow, you went to an awful lot of trouble...

I was curious. Plus I like learning from other people's mistakes. Most of the time was actually spent reading other stuff, while waiting for regenerate cores to finish. That really is excruciatingly slow. My PC is not from 2014, but it's not exactly slow either. What of course doesn't help is that xilinx in their infinite wisdom has decided that firing a "regenerate all cores" cannot be run within multiple threads. So we have 1 core with 100% utilization, and the rest is just idling. Yes, well done! I like my software to behave like software from the previous millenium.

Case in point, I think I'll see if I can write a script to parallelize that, because enough is enough. It has annoyed me in other instances as well.

I noticed that this student project version isn't the only SATA core on opencores. Another V6 version, which looks to be a project by either a working engineer/consultant or a knowledgeable hobbyist with a lot of experience. Plus I like the fact they have an AXI version available.

*bookmark*