[SOLVED] SATA controller program execution

Hello,

I have the SATA HOST controller program from the university of
massachusettes for ML405 board. However if I try to run the downloaded
project on my Xilinx ISE 14.6, it gives many errors. I am just trying to
simulate the project without connecting to the hardware. What might be
the reason for so many errors and how should it be solved?
The snapshot of the error list is attached with this file.
I actually downloaded the project file created by one Mr: Gormann from
this website.

**broken link removed**...

I have not yet connected any hardware and just wanted to run this
project on my Xilinx ISE 14.6. When I did so I got many errors. I want
yo know if its required to connect the hardware before executing this
project? Also do I need some user interface softwares like tera com,
impact to be downloaded onto my PC as I want to implement SATA read /
write. Is it possible that the entire project has not been uploaded by
the designer on the website I have listed? Please suggest about how this
problem should be solved.

I have been asked to adapt any previously written code for a SATA
controller for the ML 605 board which we have and demonstrate the read /
write capability and we donot have any purchased IP core. Please advice
on how to go about doing this?

It might help if you included the actual error message...

Also, the link you included is broken.

Not able to view the attachment...

Here is the attachment. Sorry it could not get uploaded with my previous message

http://www.ecs.umass.edu/ece/tessier/rcg/virtex4-sata/sata_core.html

This is the link

These are not errors. These are warnings. Both are different. Errors don't allow you to proceed.
The warnings are self explanatory. It is searching for a file in path. But the file is not there. Either specify your paths correctly or check whether the files are there...

Pro-tip: Get rid of that space in the "source codes" part of your directory. Spaces in paths is a source of endless fun. It's not a problem right now, but spaces in filenames are a bad habit that will cause you grief at some point.

You need to regenerate all the IP cores. All the messages you show in that screen shot are for ngc file in the project that are missing.

Take a look the hierarchy (upper left pane) and expand all the + marks so you can see all the files and where they reside in the hierarchy of the design. You should see a number of X's or ?'s that represent missing data. Either double click on them to use the ico file supplied in the project to open up coregen and re-implement each core.

Regards

can this program be executed without buying the expensive IP cores?

Just try regenerating all cores as suggested, and you will have your answer free of charge. I suspect the answer is "yes", but only you can verify this.

I regenerated all the IP cores as per your suggestions. I donot get those warnings any longer.
However when I try to simulate the behavioral model, I get some other warnings which as as shown in the screenshot. Also, this program is written for Virtex 4 FPGA. How do I change the device to Virtex 6 ML605 Evaluation board? I have also attached the screenshot of the simulation. I need to use this program for my Virtex 6 ML605 evaluation board.

when i try to change the device family from virtex 4 to virtex 6, it shows these warnings.

here is the design summary

From your target device, it looks like the project is for V4 and not V6 (I can't exactly make out from the target device).
But the warnings are shown because you have generated the core from the wrong family. You have to regenerate the core in a V6 environment.
Once you do that clean up the project environment and give a fresh run.

Hi,

I have not yet changed the target device. I am getting these compiler errors for the same target device which was mentioned by the author.

If you have not changed the target device, how did the tool get the reference to v4 as well as v6. Just check your flow once.
Regenerate the core if possible. I suppose the error has crept in here..

How did you regenerate the cores? Did you regenerate them using the original .xco files, which contains the target device. It seems like you might have inadvertently generated the cores as V6 cores. I also noticed you have two errors in translation. You should look at what those errors are by clicking on the link with the red X. Right now you've only shown the warnings and not the errors. The warnings might just be nothing, but the error is what stops the build flow.

Hi,

I opened COREGEN GUI and opened the project with coregen file(.cgp) and then said regenerate cores.

i HAVE NOW TRIED TO REGENERATE THE CORES DDIRECTLY FROM ise. tHE MISSING FILES ARE GONE. hOWEVER IT SHOWS SOME ERRORS. cAN YOU TELL ME WHAT THESE ERRORS MIGHT BE DUE TO?

- - - Updated - - -

here is my entire project. Please help me resolve the errors

Your problem is both the simulation and the synthesis version of each core is included in the project and they are both getting compiled regardless if you are running simulation or synthesis. I'm wondering how you added the IP cores into the project as I've never seen this happen before.

I don't regularly use the ISE GUI as I prefer to script both my builds and simulation. So I'm not sure where you fix this problem in the GUI and assign which version of the file is compiled depending on whether you are in simulation or implementation mode.

One option is to remove all the xco files and add the ngc files for each core instead, though this might break running simulations from the GUI as it might not be able to compile the correct simulation RTL.