SAR ADC unit cap selection

Hi,

I have seen in some papers that for SAR ADCs with 10 to 12 bit resolution, the unit cap was chosen pretty small (ranging from 4fF to 40fF). Though this value satisfies the thermal noise, or matching requirement, but to me there should be a problem with input capacitance of the comparator.
For such resolutions, the input pair of the comparator can't be small (due to thermal, flicker, and mismatch requirements), so input cap would be large. Part of this input cap would be input dependent and will cause non linearity effects, so INL or DNL would be large. However, I have seen some works with small unit cap that they reported acceptable DNL. I am kinda confused, is there something I'm missing?

It does sound unusual, but then this is a research paper.

It could be an exotic process using 40nm CMOS with some critical stray capacitance scheme using a Capacitive DAC in C-2C mode rather than R-2R resistive mode at microwave speeds.

Any references?

SunnySkyguy said:

It does sound unusual, but then this is a research paper.

It could be an exotic process using 40nm CMOS with some critical stray capacitance scheme using a Capacitive DAC in C-2C mode rather than R-2R resistive mode at microwave speeds.

Any references?

Click to expand...

Thanks for your comment. Actually most of them are published in JSSC, so I guess they are kinda reliable. I just picked some of them, there are more recent papers but since they changed the structure of the ADC a bit, I didn't list them here
A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13- m CMOS for Medical Implant Devices: JSSC'12------Unit Cap = 13.5 fF-------Process = 0.13um
-----------------------------
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure : JSSC'10 ------Unit Cap = 4.8fF -------Process = 0.13um
-----------------------
A 10-bit 50-MS/s redundant SAR ADC with split capacitive-array DAC : Springer'12 -------Unit Cap = 20fF -----Process = 0.18um
-----------------------------

Hi,

I think the cap in the summing node had better consider all DAC array cap. In the 10-bit 50Ms/s case, the cap in one branch is 2^10=1024*unit=4.9p, which should be much larger than one comparator input transistor parasitic cap.

Hope this is helpful.

Thanks
Daniel

dan_vol said:

... the cap in one branch is 2^10=1024*unit=4.9p, which should be much larger than one comparator input transistor parasitic cap.

Hope this is helpful.

Click to expand...

Not too much, sorry.
This is true for the MSB comparison - but what about the LSB comparison with 2¹=2 unit caps = 9.6fF?

mordak said:

Thanks for your comment. Actually most of them are published in JSSC, so I guess they are kinda reliable. I just picked some of them, there are more recent papers but since they changed the structure of the ADC a bit, I didn't list them here
A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13- m CMOS for Medical Implant Devices: JSSC'12------Unit Cap = 13.5 fF-------Process = 0.13um
---------------------------= 0.18um
-----------------------------

Click to expand...

10 bit 50MHz sampling rate implies a 500MHz SAR rate or more which sounds ok or 180nm CMOS.

The C ratio method is the way to go at these rates. Then 40nm might yield 2GHz rates.

Process controls of C ratio tolerances and dielectric selection are the key to success here.


-Compare with http://cds.linear.com/docs/en/datasheet/226114fc.pdf

erikl said:

Not too much, sorry.
This is true for the MSB comparison - but what about the LSB comparison with 2¹=2 unit caps = 9.6fF?

Click to expand...

Thank you for your reply.

Yeah, you are right. In the LSB comparison, the comparator input parasitic cap may be comparable with unit cap. But if it's maintained below, let's assume, 1 unit cap. I think, it should be OK for the resolution. In this case, we may assume input parasitic cap=4.8f. And the problem may be whether this width is enough for thermal, flicker noise, speed and offset. For the thermal noise, KT/C seems enough, since cap at the input is 4.9p. For the speed, that depends on the process and latch's structure. And offset due to mismatch will cause a DC shift at the output, which can be digitally calibrated in digital output. For the flicker noise, I am not sure. I think, maybe for the frequency here, still the thermal noise is predominant.

And I have checked the first paper you mentioned. In the dynamic comparator section, they mentions the thermal noise is the fundamental noise cause. And they measured comparator's post-layout output cap is 10f, where I don't understand why it's output cap ,not the input cap.

In conclusion, I am not sure about the flicker noise and output cap. And I think width of comparators' input transistors may not need to be that large.

Thanks
Daniel